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When we used OpenROAD to read Cadence Innovus's generated DEF after global placement, we received incorrect delay results. I attached the detailed timing path info below, can you help guide us on what we need to check/set to solve the problem? Thanks for your help.
The design is Vortex Large design in CircuitNet, we also conducted a Small Boom design and observed a similar issue.
Read DEF that is generated by Cadence Innovus after global placement.
Read LIB/LEF/SDC and set layer rc and wire rc.
report_wns / report_tns, the outputs in the terminal are as follows:
[INFO ODB-0127] Reading DEF file: s14_vortex_large.def
[INFO ODB-0128] Design: Vortex
[INFO ODB-0094] Created 100000 Insts
[INFO ODB-0094] Created 200000 Insts
[INFO ODB-0094] Created 300000 Insts
[INFO ODB-0094] Created 400000 Insts
[INFO ODB-0094] Created 500000 Insts
[INFO ODB-0094] Created 600000 Insts
[INFO ODB-0094] Created 700000 Insts
[INFO ODB-0097] Created 100000 Nets
[INFO ODB-0097] Created 200000 Nets
[INFO ODB-0097] Created 300000 Nets
[INFO ODB-0097] Created 400000 Nets
[INFO ODB-0097] Created 500000 Nets
[INFO ODB-0097] Created 600000 Nets
[INFO ODB-0097] Created 700000 Nets
[INFO ODB-0097] Created 800000 Nets
[INFO ODB-0130] Created 1242 pins.
[INFO ODB-0131] Created 771100 components and 6024379 component-terminals.
[INFO ODB-0132] Created 2 special nets and 1542200 connections.
[INFO ODB-0133] Created 827446 nets and 2938764 connections.
[INFO ODB-0134] Finished DEF file: s14_vortex_large.def
Design area 773486 u^2 53% utilization.
wns -16796331155855432494719871073432633344.00
tns -INF
We uploaded screenshots of OpenROAD timing reports inGoogleDrive, please refer to.
The abnormal slew values in a timing path in pictures are observed in a cell with type "AOI22V1 9OS9T1GR", the input slew is 0.145 (valid range is [0, 1]), and the output load is 0.01 (valid range is [1e-8, 1], the output slew is a huge abnormal value (please refer to the https://drive.google.com/file/d/1EoF0XDiHdCor-3q9sBRJ3GYcLalFRrga/view?usp=drive_link).
Expected Behavior
Correct cell delay calculated by OpenROAD/OpenSTA
Environment
We used openraod-flow-scripts to build a docker.
To Reproduce
read def/lef/lib/sdc
set layer wire rc
estimate_parasitics -placement
report_design_area
report_wns
report_tns
Relevant log output
[INFO ODB-0127] Reading DEF file: s14_vortex_large.def
[INFO ODB-0128] Design: Vortex
[INFO ODB-0094] Created 100000 Insts
[INFO ODB-0094] Created 200000 Insts
[INFO ODB-0094] Created 300000 Insts
[INFO ODB-0094] Created 400000 Insts
[INFO ODB-0094] Created 500000 Insts
[INFO ODB-0094] Created 600000 Insts
[INFO ODB-0094] Created 700000 Insts
[INFO ODB-0097] Created 100000 Nets
[INFO ODB-0097] Created 200000 Nets
[INFO ODB-0097] Created 300000 Nets
[INFO ODB-0097] Created 400000 Nets
[INFO ODB-0097] Created 500000 Nets
[INFO ODB-0097] Created 600000 Nets
[INFO ODB-0097] Created 700000 Nets
[INFO ODB-0097] Created 800000 Nets
[INFO ODB-0130] Created 1242 pins.
[INFO ODB-0131] Created 771100 components and 6024379 component-terminals.
[INFO ODB-0132] Created 2 special nets and 1542200 connections.
[INFO ODB-0133] Created 827446 nets and 2938764 connections.
[INFO ODB-0134] Finished DEF file: s14_vortex_large.def
Design area 773486 u^2 53% utilization.
wns -16796331155855432494719871073432633344.00
tns -INF
Screenshots
We uploaded screenshots of OpenROAD timing reports inGoogleDrive, please refer to.
The abnormal slew values in a timing path in pictures are observed in a cell with type "AOI22V1 9OS9T1GR", the input slew is 0.145, and the output load is 0.01, which are in the range of index of Lookup table in the cell. the output slew is a huge abnormal value (please refer to the https://drive.google.com/file/d/1EoF0XDiHdCor-3q9sBRJ3GYcLalFRrga/view?usp=drive_link).
Additional Context
No response
The text was updated successfully, but these errors were encountered:
Describe the bug
Dear developers,
When we used OpenROAD to read Cadence Innovus's generated DEF after global placement, we received incorrect delay results. I attached the detailed timing path info below, can you help guide us on what we need to check/set to solve the problem? Thanks for your help.
The design is Vortex Large design in CircuitNet, we also conducted a Small Boom design and observed a similar issue.
Expected Behavior
Correct cell delay calculated by OpenROAD/OpenSTA
Environment
To Reproduce
Relevant log output
Screenshots
We uploaded screenshots of OpenROAD timing reports inGoogleDrive, please refer to.
Additional Context
No response
The text was updated successfully, but these errors were encountered: