How to Feed Data Into FINN IP Block and Interpret the Output?

[unnamed-002]

I followed the steps from this link:
https://github.com/jterry-x/finn-examples/tree/main/build/fpga_flow

I added the output_tfc_w1a1_fpga/stitched_ip/ip folder to my repository and got a stitched IP block named finn_design_0.

Next, I connected the stitched IP block to an AXI4-Stream Data FIFO because TLAST is required by the DMA. My setup is a MicroBlaze system using Nexys 4 DDR.

The bitstream was generated successfully with this Critical Warning:
[Designutils 20-1275] Could not find cell 'inst' within module 'design_1_finn_design_0_0' for instance 'design_1_i/finn_design_0'. The XDC file ../sources_1/bd/design_1/ip/design_1_finn_design_0_0/impl/finn_design.xdc will not be read for this cell.

However, I'm stuck on what to do next, like how do I get data out of the FINN IP block? Is there any simple code example that shows what kind of data I should feed into it and what to expect as output?

Any help or guidance would be greatly appreciated!

[fpjentzsch]

Hi,
you could look at how the FINN-generated PYNQ driver interacts with the FINN DMAs for the input and output stream:

finn/src/finn/qnn-data/templates/driver/driver_base.py

Line 397 in ee29287

def execute(self, input_npy):

The full FINN build flow will generate an io_shape_dict (in driver.py) for your accelerator according to your bit widths and folding parameters. The driver then arranges/packs the data accordingly, places it in DRAM, and instructs the DMAs to start the transfers.

[unnamed-002]

Thanks for your comment. I'll take a look at it.

[JPPalacios]

Hi @unnamed-002,

Any luck with implementing changes? Did you place a FIFO before or after your FINN-generated IP?

[unnamed-002]

Hi @JPPalacios
I placed the FIFO after the FINN stitched IP, but I couldn’t get it to work. I’ve since put the task aside for now. In case you’re wondering, I came across someone who successfully implemented FIFO with the FINN stitched IP. You can check out his approach here: https://github.com/0BAB1/BRH_Tutorials/tree/main/8%20Python%20to%20FPGA/3_manual_inference