Dose BAO linux+freertos supported GDB on arm64 virtual platform?

[JosonFD]

I want to used GDB to debug VM linux,how to configure?

[josecm]

Hey Joson, I assume that by "virtual platforms" you are referring to the FVP Models. In those platforms I have always used the arm debugger that comes with Arm development studio. I think the question ir more regarding the models than Bao itself. So I don't think I can help you setup GDB with the models.

[JosonFD]

Hey Joson, I assume that by "virtual platforms" you are referring to the FVP Models. In those platforms I have always used the arm debugger that comes with Arm development studio. I think the question ir more regarding the models than Bao itself. So I don't think I can help you setup GDB with the models.

Hello, Josecm, thank you very much for your reply!
Currently, I have two questions:
My question is about how to use GDB to debug BAO HYPERVISOR + LINUX on the QEMU emulation platform. How should I configure it? Could you provide a corresponding tutorial repository?
I am adapting our BAO to run on the Phytium D2000(armv8 a73*8,gicv3,) hardware platform and running virtual machines with Linux + FreeRTOS. I encountered an issue where there is no output after jumping to Linux. I suspect the problem happens in the assembly head.S stage. I am currently using UART for debugging, but when entering Linux, after __enable_mmu function, the serial port stops working. When mapping the UART device address in the virtual machine, how should I configure it in stage1 page manage, especially in head.S?
Looking forward to your reply, and thank you very much!

[josecm]

Could you provide a corresponding tutorial repository?

We do not have any guides on debugging bao. But in our experience simply adding the symbol file (vmlinux, but you must compile linux with the debug options enabled).

I suspect your issue has something to do with the configuration you are giving Bao and maybe a mismatch with the device tree you are giving Linux. Could you provide these files so maybe we could help you out.

[JosonFD]

Device Tree Configuration for Serial Output (PL011 UART, Base Address 0x28001000)
I want to configure device tree to use the PL011 UART at the base address 0x28001000 for serial debugging output. Below is the device tree configuration for this purpose:
`/dts-v1/;

/ {
#size-cells = <0x2>;
#address-cells = <0x2>;

cpus {
	#size-cells = <0x0>;
	#address-cells = <0x1>;

	cpu@0 {
		compatible = "phytium,ftc663\0arm,armv8";
		device_type = "cpu";
		enable-method = "psci";
		reg = <0x0>;
	};
};

psci {
	compatible = "arm,psci-1.0";
	method = "smc";
};


memory@90000000 {
	reg = <0x0 0x90000000 0x0 0x40000000>;
	device_type = "memory";
};

gic: intc@29000000 {
	interrupts = <0x01 0x09 0x04>;
	reg = <0x00 0x29000000 0x00 0x60000 0x00 0x29100000 0x00 0x2000>;
	#redistributor-regions = <0x01>;
	compatible = "phytium,d2000-ixic";
	interrupt-controller;
	#interrupt-cells = <0x03>;
    interrupt-parent = <&gic>;
};

timer {
	compatible = "arm,armv8-timer";
	interrupt-parent = <&gic>;
	interrupts = <0x01 0x0d 0x08 0x01 0x0e 0x08 0x01 0x0b 0x08 0x01 0x0a 0x08>;
};

uartclk: uartclk {
	compatible = "fixed-clock";
	#clock-cells = <0x0>;
	clock-frequency = <0x2dc6c00>;
	phandle = <0x1>;
};

	bao-ipc@f0000000 {
    	compatible = "bao,ipcshmem";
    	reg = <0x0 0xf0000000 0x0 0x00010000>;
	read-channel = <0x0 0x2000>;
	write-channel = <0x2000 0x2000>;
    	interrupts = <0 52 1>;
	interrupt-parent = <&gic>;
	id = <0>;
	};

uart@28001000 {
		compatible = "arm,pl011\0arm,primecell";
		status = "ok";
		interrupts = <0x00 0x07 0x04>;
		reg = <0x00 0x28001000 0x00 0x1000>;
		clock-names = "uartclk\0apb_pclk";
		clocks = <0x03 0x03>;
};

aliases {
	serial1 = "uart@28001000";
};

chosen {
	bootargs = "earlycon console=ttyAMA1,115200n8 clk_ignore_unused ip=192.168.42.15 carrier_timeout=0";
	stdout-path = "serial1:115200n8";
};

};`

[JosonFD]

Could you provide a corresponding tutorial repository?

We do not have any guides on debugging bao. But in our experience simply adding the symbol file (vmlinux, but you must compile linux with the debug options enabled).

I suspect your issue has something to do with the configuration you are giving Bao and maybe a mismatch with the device tree you are giving Linux. Could you provide these files so maybe we could help you out.

The original runnable device tree is as follows.

`/ {
compatible = "phytium,d2000";
interrupt-parent = <0x00000001>;
#address-cells = <0x00000002>;
#size-cells = <0x00000002>;
model = "D2000 Development Board";
reserved-memory {
#address-cells = <0x00000002>;
#size-cells = <0x00000002>;
ranges;
reserved@b0000000 {
reg = <0x00000000 0xb0000000 0x00000000 0x10000000>;
no-map;
};
};
aliases {
ethernet0 = "/soc/eth@2820c000";
ethernet1 = "/soc/eth@28210000";
};
psci {
compatible = "arm,psci-1.0";
method = "smc";
cpu_suspend = <0xc4000001>;
cpu_off = <0x84000002>;
cpu_on = <0xc4000003>;
sys_poweroff = <0x84000008>;
sys_reset = <0x84000009>;
};
cpus {
#address-cells = <0x00000002>;
#size-cells = <0x00000000>;
cpu@0 {
device_type = "cpu";
compatible = "arm,armv8";
reg = <0x00000000 0x00000000>;
enable-method = "psci";
numa-node-id = <0x00000000>;
clocks = <0x00000002 0x00000000>;
};
cpu@1 {
device_type = "cpu";
compatible = "arm,armv8";
reg = <0x00000000 0x00000001>;
enable-method = "psci";
numa-node-id = <0x00000000>;
clocks = <0x00000002 0x00000000>;
};
cpu@100 {
device_type = "cpu";
compatible = "arm,armv8";
reg = <0x00000000 0x00000100>;
enable-method = "psci";
numa-node-id = <0x00000000>;
clocks = <0x00000002 0x00000001>;
};
cpu@101 {
device_type = "cpu";
compatible = "arm,armv8";
reg = <0x00000000 0x00000101>;
enable-method = "psci";
numa-node-id = <0x00000000>;
clocks = <0x00000002 0x00000001>;
};
cpu@200 {
device_type = "cpu";
compatible = "arm,armv8";
reg = <0x00000000 0x00000200>;
enable-method = "psci";
numa-node-id = <0x00000000>;
clocks = <0x00000002 0x00000002>;
};
cpu@201 {
device_type = "cpu";
compatible = "arm,armv8";
reg = <0x00000000 0x00000201>;
enable-method = "psci";
numa-node-id = <0x00000000>;
clocks = <0x00000002 0x00000002>;
};
cpu@300 {
device_type = "cpu";
compatible = "arm,armv8";
reg = <0x00000000 0x00000300>;
enable-method = "psci";
numa-node-id = <0x00000000>;
clocks = <0x00000002 0x00000003>;
};
cpu@301 {
device_type = "cpu";
compatible = "arm,armv8";
reg = <0x00000000 0x00000301>;
enable-method = "psci";
numa-node-id = <0x00000000>;
clocks = <0x00000002 0x00000003>;
};
};
interrupt-controller@29900000 {
compatible = "arm,gic-v3";
#interrupt-cells = <0x00000003>;
#address-cells = <0x00000002>;
#size-cells = <0x00000002>;
ranges;
interrupt-controller;
reg = * 0x00000000fae41704 [0x00000050];
interrupts = <0x00000001 0x00000009 0x00000004>;
phandle = <0x00000001>;
gic-its@29920000 {
compatible = "arm,gic-v3-its";
msi-controller;
reg = <0x00000000 0x29a20000 0x00000000 0x00020000>;
phandle = <0x00000009>;
};
};
timer {
compatible = "arm,armv8-timer";
interrupts = <0x00000001 0x0000000d 0x00000008 0x00000001 0x0000000e 0x00000008 0x00000001 0x0000000b 0x00000008 0x00000001 0x0000000a 0x00000008>;
clock-frequency = <0x02dc6c00>;
};
pmu {
compatible = "arm,armv8-pmuv3";
interrupts = <0x00000001 0x00000007 0x00000008>;
};
clocks {
#address-cells = <0x00000002>;
#size-cells = <0x00000002>;
ranges;
clk250mhz {
compatible = "fixed-clock";
#clock-cells = <0x00000000>;
clock-frequency = <0x0ee6b280>;
phandle = <0x00000005>;
};
clk48mhz {
compatible = "fixed-clock";
#clock-cells = <0x00000000>;
clock-frequency = <0x02dc6c00>;
phandle = <0x00000003>;
};
clk600mhz {
compatible = "fixed-clock";
#clock-cells = <0x00000000>;
clock-frequency = "#

                                                            phandle = <0x00000004>;
            };
    };
    soc {
            compatible = "simple-bus";
            #address-cells = <0x00000002>;
            #size-cells = <0x00000002>;
            dma-coherent;
            ranges;
            gpio@28004000 {
                    compatible = "phytium,gpio";
                    reg = <0x00000000 0x28004000 0x00000000 0x00001000>;
                    interrupts = <0x00000000 0x0000000a 0x00000004>;
                    gpio-controller;
                    #gpio-cells = <0x00000002>;
                    #address-cells = <0x00000001>;
                    #size-cells = <0x00000000>;
                    porta {
                            compatible = "phytium,gpio-port";
                            reg = <0x00000000>;
                            nr-gpios = <0x00000008>;
                    };
                    portb {
                            compatible = "phytium,gpio-port";
                            reg = <0x00000001>;
                            nr-gpios = <0x00000008>;
                    };
            };
            gpio@28005000 {
                    compatible = "phytium,gpio";
                    reg = <0x00000000 0x28005000 0x00000000 0x00001000>;
                    interrupts = <0x00000000 0x0000000b 0x00000004>;
                    gpio-controller;
                    #gpio-cells = <0x00000002>;
                    #address-cells = <0x00000001>;
                    #size-cells = <0x00000000>;
                    porta {
                            compatible = "phytium,gpio-port";
                            reg = <0x00000000>;
                            nr-gpios = <0x00000008>;
                    };
                    portb {
                            compatible = "phytium,gpio-port";
                            reg = <0x00000001>;
                            nr-gpios = <0x00000008>;
                    };
            };
            uart@28000000 {
                    compatible = "arm,pl011", "arm,primecell";
                    reg = <0x00000000 0x28000000 0x00000000 0x00001000>;
                    baud = <0x0001c200>;
                    reg-shift = <0x00000002>;
                    reg-io-width = <0x00000004>;
                    interrupts = <0x00000000 0x00000006 0x00000004>;
                    clocks = <0x00000003 0x00000003>;
                    clock-names = "uartclk", "apb_pclk";
            };
            uart@28001000 {
                    compatible = "arm,pl011", "arm,primecell";
                    reg = <0x00000000 0x28001000 0x00000000 0x00001000>;
                    baud = <0x0001c200>;
                    reg-shift = <0x00000002>;
                    reg-io-width = <0x00000004>;
                    interrupts = <0x00000000 0x00000007 0x00000004>;
                    clocks = <0x00000003 0x00000003>;
                    clock-names = "uartclk", "apb_pclk";
                    status = "ok";
            };
            uart@28002000 {
                    compatible = "arm,pl011", "arm,primecell";
                    reg = <0x00000000 0x28002000 0x00000000 0x00001000>;
                    baud = <0x0001c200>;
                    reg-shift = <0x00000002>;
                    reg-io-width = <0x00000004>;
                    interrupts = <0x00000000 0x00000008 0x00000004>;
                    clocks = <0x00000003 0x00000003>;
                    clock-names = "uartclk", "apb_pclk";
            };
            uart@28003000 {
                    compatible = "arm,pl011", "arm,primecell";
                    reg = <0x00000000 0x28003000 0x00000000 0x00001000>;
                    baud = <0x0001c200>;
                    reg-shift = <0x00000002>;
                    reg-io-width = <0x00000004>;
                    interrupts = <0x00000000 0x00000009 0x00000004>;
                    clocks = <0x00000003 0x00000003>;
                    clock-names = "uartclk", "apb_pclk";
            };
            sdci@28207c00 {
                    compatible = "phytium,sdci";
                    reg = <0x00000000 0x28207c00 0x00000000 0x00000100>;
                    interrupts = <0x00000000 0x00000014 0x00000004 0x00000000 0x00000015 0x00000004 0x00000000 0x00000016 0x00000004>;
                    clocks = <0x00000004 0x00000004>;
                    clock-names = "phytium_sdc_clk";
                    no-sdio;
                    no-mmc;
                    no-dma-coherent;
            };
            watchdog@2800a000 {
                    compatible = "arm,sbsa-gwdt";
                    reg = <0x00000000 0x2800b000 0x00000000 0x00001000 0x00000000 0x2800a000 0x00000000 0x00001000>;
                    interrupts = <0x00000000 0x00000010 0x00000004>;
                    timeout-sec = <0x0000001e>;
            };
            watchdog@28016000 {
                    compatible = "arm,sbsa-gwdt";
                    reg = <0x00000000 0x28017000 0x00000000 0x00001000 0x00000000 0x28016000 0x00000000 0x00001000>;
                    interrupts = <0x00000000 0x00000011 0x00000004>;
                    timeout-sec = <0x0000001e>;
            };
            rtc@2800d000 {
                    compatible = "phytium,rtc";
                    reg = <0x00000000 0x2800d000 0x00000000 0x00001000>;
                    clocks = <0x00000003>;
                    clock-names = "rtc_pclk";
                    interrupts = <0x00000000 0x00000004 0x00000004>;
                    status = "ok";
            };
            i2c@28006000 {
                    compatible = "snps,designware-i2c";
                    reg = <0x00000000 0x28006000 0x00000000 0x00001000>;
                    interrupts = <0x00000000 0x0000000c 0x00000004>;
                    clocks = <0x00000003>;
                    status = "ok";
            };
            i2c@28007000 {
                    compatible = "snps,designware-i2c";
                    reg = <0x00000000 0x28007000 0x00000000 0x00001000>;
                    interrupts = <0x00000000 0x0000000d 0x00000004>;
                    clocks = <0x00000003>;
                    status = "ok";
                    #address-cells = <0x00000001>;
                    #size-cells = <0x00000000>;
                    rtc@68 {
                            compatible = "dallas,ds1339";
                            reg = <0x00000068>;
                    };
            };
            i2c@28008000 {
                    compatible = "snps,designware-i2c";
                    reg = <0x00000000 0x28008000 0x00000000 0x00001000>;
                    interrupts = <0x00000000 0x0000000e 0x00000004>;
                    clocks = <0x00000003>;
                    status = "disabled";
            };
            i2c@28009000 {
                    compatible = "snps,designware-i2c";
                    reg = <0x00000000 0x28009000 0x00000000 0x00001000>;
                    interrupts = <0x00000000 0x0000000f 0x00000004>;
                    clocks = <0x00000003>;
                    status = "disabled";
            };
            spi@2800c000 {
                    compatible = "phytium,spi";
                    interrupts = <0x00000000 0x00000012 0x00000004>;
                    reg = <0x00000000 0x2800c000 0x00000000 0x00001000>;
                    clocks = <0x00000003>;
                    num-cs = <0x00000004>;
                    status = "ok";
            };
            spi@28013000 {
                    compatible = "phytium,spi";
                    interrupts = <0x00000000 0x00000013 0x00000004>;
                    reg = <0x00000000 0x28013000 0x00000000 0x00001000>;
                    clocks = <0x00000003>;
                    num-cs = <0x00000004>;
            };
            qspi@28014000 {
                    compatible = "phytium,qspi";
                    reg = <0x00000000 0x28014000 0x00000000 0x00001000 0x00000000 0x00000000 0x00000000 0x02000000>;
                    reg-names = "qspi", "qspi_mm";
                    clocks = <0x00000004>;
                    status = "ok";
                    flash@0 {
                            spi-rx-bus-width = <0x00000001>;
                            spi-max-frequency = "#

                                                                    };
            };
            stmmac-axi-config {
                    snps,wr_osr_lmt = <0x00000000>;
                    snps,rd_osr_lmt = <0x00000000>;
                    snps,blen = <0x00000000 0x00000000 0x00000000 0x00000000 0x00000010 0x00000008 0x00000004>;
                    phandle = <0x00000006>;
            };
            eth@2820c000 {
                    local-mac-address = [3c 6a 2c 3c 6a dd];
                    compatible = "snps,dwmac";
                    reg = <0x00000000 0x2820c000 0x00000000 0x00002000>;
                    interrupts = <0x00000000 0x00000031 0x00000004>;
                    interrupt-names = "macirq";
                    clocks = <0x00000005>;
                    clock-names = "stmmaceth";
                    status = "ok";
                    snps,pbl = <0x00000010>;
                    snps,fixed-burst;
                    snps,axi-config = <0x00000006>;
                    snps,force_sf_dma_mode;
                    snps,multicast-filter-bins = <0x00000040>;
                    snps,perfect-filter-entries = <0x00000080>;
                    tx-fifo-depth = <0x00001000>;
                    rx-fifo-depth = <0x00001000>;
                    max-frame-size = <0x00002328>;
                    phy-mode = "rgmii-txid";
            };
            eth@28210000 {
                    local-mac-address = [3c 6a 2c 3c 6a bb];
                    compatible = "snps,dwmac";
                    reg = <0x00000000 0x28210000 0x00000000 0x00002000>;
                    interrupts = <0x00000000 0x00000032 0x00000004>;
                    interrupt-names = "macirq";
                    clocks = <0x00000005>;
                    clock-names = "stmmaceth";
                    status = "ok";
                    snps,pbl = <0x00000010>;
                    snps,fixed-burst;
                    snps,axi-config = <0x00000006>;
                    snps,force_sf_dma_mode;
                    snps,multicast-filter-bins = <0x00000040>;
                    snps,perfect-filter-entries = <0x00000080>;
                    snps,rx-queues-to-use = <0x00000002>;
                    tx-fifo-depth = <0x00001000>;
                    rx-fifo-depth = <0x00001000>;
                    max-frame-size = <0x00002328>;
                    phy-mode = "rgmii-txid";
            };
            can@28207000 {
                    compatible = "phytium,can";
                    reg = <0x00000000 0x28207000 0x00000000 0x00000400>;
                    interrupts = <0x00000000 0x00000057 0x00000004>;
                    clocks = <0x00000004>;
                    clock-names = "phytium_can_clk";
                    tx-fifo-depth = <0x00000040>;
                    rx-fifo-depth = <0x00000040>;
            };
            can@28207400 {
                    compatible = "phytium,can";
                    reg = <0x00000000 0x28207400 0x00000000 0x00000400>;
                    interrupts = <0x00000000 0x0000005b 0x00000004>;
                    clocks = <0x00000004>;
                    clock-names = "phytium_can_clk";
                    tx-fifo-depth = <0x00000040>;
                    rx-fifo-depth = <0x00000040>;
            };
            can@028207800 {
                    compatible = "phytium,can";
                    reg = <0x00000000 0x28207800 0x00000000 0x00000400>;
                    interrupts = <0x00000000 0x0000005c 0x00000004>;
                    clocks = <0x00000004>;
                    clock-names = "phytium_can_clk";
                    tx-fifo-depth = <0x00000040>;
                    rx-fifo-depth = <0x00000040>;
            };
            hda@28206000 {
                    compatible = "phytium,hda";
                    reg = <0x00000000 0x28206000 0x00000000 0x00001000>;
                    interrupts = <0x00000000 0x00000017 0x00000004>;
                    clocks = <0x00000003>;
                    clock-names = "phytium_hda_clk";
            };
            mailbox@2a000000 {
                    compatible = "phytium,mbox";
                    reg = <0x00000000 0x2a000000 0x00000000 0x00001000>;
                    interrupts = <0x00000000 0x00000030 0x00000004>;
                    #mbox-cells = <0x00000001>;
                    clocks = <0x00000003>;
                    clock-names = "apb_pclk";
                    phandle = <0x00000007>;
            };
            sram@2a006000 {
                    compatible = "phytium,ft2004-sram-ns", "mmio-sram";
                    reg = <0x00000000 0x2a006000 0x00000000 0x00002000>;
                    #address-cells = <0x00000001>;
                    #size-cells = <0x00000001>;
                    ranges = <0x00000000 0x00000000 0x2a006000 0x00002000>;
                    scpi-shmem@0 {
                            compatible = "phytium,ft2004-scpi-shmem";
                            reg = <0x00001000 0x00000800>;
                            phandle = <0x00000008>;
                    };
            };
            scpi {
                    compatible = "arm,scpi";
                    mboxes = <0x00000007 0x00000000>;
                    shmem = <0x00000008>;
                    clocks {
                            compatible = "arm,scpi-clocks";
                            scpi_clocks@0 {
                                    compatible = "arm,scpi-dvfs-clocks";
                                    #clock-cells = <0x00000001>;
                                    clock-indices = <0x00000000 0x00000001 0x00000002 0x00000003>;
                                    clock-output-names = "c0", "c1", "c2", "c3";
                                    phandle = <0x00000002>;
                            };
                    };
                    sensors {
                            compatible = "arm,scpi-sensors";
                            #thermal-sensor-cells = <0x00000001>;
                    };
            };
            interrupt-controller@29000000 {
                    compatible = "phytium,d2000-ixic";
                    reg-names = "ctr", "hpb";
                    reg = <0x00000000 0x29000000 0x00000000 0x00060000 0x00000000 0x29100000 0x00000000 0x00002000>;
                    interrupt-controller;
                    interrupt-parent = <0x00000001>;
                    #interrupt-cells = <0x00000003>;
                    intx-spi-base = <0x0000001c>;
                    phandle = <0x0000000a>;
            };
            pcie {
                    compatible = "pci-host-ecam-generic";
                    device_type = "pci";
                    #address-cells = <0x00000003>;
                    #size-cells = <0x00000002>;
                    #interrupt-cells = <0x00000001>;
                    reg = <0x00000000 0x40000000 0x00000000 0x10000000>;
                    msi-parent = <0x00000009>;
                    bus-range = <0x00000000 0x000000ff>;
                    interrupt-map-mask = <0x00000000 0x00000000 0x00000000 0x00000007>;
                    interrupt-map = * 0x00000000fae431d8 [0x00000080];
                    ranges = * 0x00000000fae43264 [0x00000054];
            };
    };
    chosen {
            bootargs = "console=ttyAMA1,115200 earlycon=pl011,0x28001000 root=/dev/sda4 rootdelay=5 rw";
            stdout-path = "uart1:115200n8";
    };
    memory@00 {
            device_type = "memory";
            reg = <0x00000000 0x80000000 0x00000000 0x7b000000>;
    };
    memory@01 {
            device_type = "memory";
            reg = <0x00000020 0x00000000 0x00000003 0x80000000>;
    };
    firmware {
            optee {
                    compatible = "linaro,optee-tz";
                    method = "smc";
            };
    };

};
`