Assertion error with F4PGA-produced .fasm

[wkkuna]

I get the following error when trying to run fasm2bels with the design I wanted to debug (that was successfully built with F4PGA):

(symbiflow_xc_fasm2bels) wkuna@Terassen:~/bigboy/F4PGA/f4pga-xc-fasm2bels$ python -mfasm2bels --connection_database ../f4pga-arch-defs/build/xc/xc7/archs/zynq7_z020/channels/xc7z020clg484-1/channels.db  --db_root ../prjxray-db/zynq7/ --part xc7z020clg484-1 --rr_graph ../../../opt/f4pga/xc7/install/share/symbiflow/arch/xc7z020_test/rr_graph_xc7z020_test.rr_graph.real.bin  --vpr_grid_map ../../../opt/f4pga/xc7/install/share/symbiflow/arch/xc7z020_test/vpr_grid_map.csv --fasm_file ../../../fpga-isp/litex/build/zynq_video_board/gateware/zynq_video_board.fasm 
Traceback (most recent call last):
  File "/home/wkuna/bigboy/F4PGA/f4pga-xc-fasm2bels/env/conda/envs/symbiflow_xc_fasm2bels/lib/python3.8/runpy.py", line 194, in _run_module_as_main
    return _run_code(code, main_globals, None,
  File "/home/wkuna/bigboy/F4PGA/f4pga-xc-fasm2bels/env/conda/envs/symbiflow_xc_fasm2bels/lib/python3.8/runpy.py", line 87, in _run_code
    exec(code, run_globals)
  File "/home/wkuna/bigboy/F4PGA/f4pga-xc-fasm2bels/fasm2bels/__main__.py", line 15, in <module>
    main()
  File "/home/wkuna/bigboy/F4PGA/f4pga-xc-fasm2bels/fasm2bels/fasm2bels.py", line 475, in main
    process_tile(top, tile, tile_features)
  File "/home/wkuna/bigboy/F4PGA/f4pga-xc-fasm2bels/fasm2bels/fasm2bels.py", line 139, in process_tile
    PROCESS_TILE[tile_type](top.conn, top, tile, tile_features)
  File "/home/wkuna/bigboy/F4PGA/f4pga-xc-fasm2bels/fasm2bels/models/clb_models.py", line 2079, in process_clb
    process_slice(top, slices[s])
  File "/home/wkuna/bigboy/F4PGA/f4pga-xc-fasm2bels/fasm2bels/models/clb_models.py", line 1840, in process_slice
    assert False, site.features
AssertionError: {'ALUT.INIT', 'AOUTMUX.O5', 'COUTMUX.O5', 'CLUT.INIT'}

The rr_graph, connection_database, vpr_grid_map were from the f4pga-arch-defs build at commit 7d521273b82a0 the prjxray-bd at commit 0a0addedd73e7.

I include fasm file that was generated via F4PGA with LiteX zynq_video_board.fasm.log

[zliu1Charlotte]

Hi how did you generate this? thanks!
--connection_database ../f4pga-arch-defs/build/xc/xc7/archs/zynq7_z020/channels/xc7z020clg484-1/channels.db