forked from ashishrana160796/verilog-starter-tutorials
-
Notifications
You must be signed in to change notification settings - Fork 0
/
Copy pathEncoder4x2.v
48 lines (39 loc) · 838 Bytes
/
Encoder4x2.v
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
module enc(in,ou);
input [3:0] in;
output [1:0] ou;
reg [1:0] ou;
always@(*)
begin
case(in)
4'b0001:
ou = 2'b00;
4'b0010:
ou = 2'b01;
4'b0100:
ou = 2'b10;
4'b1000:
ou = 2'b11;
endcase
end
endmodule
module test;
reg [3:0] inline;
wire [1:0] oline;
enc e(inline,oline);
initial
begin
$display("input and output show");
$monitor("%b,%b,%b,%b,%b,%b",inline[3],inline[2],inline[1],inline[0],oline[1],oline[0]);
$dumpfile("vcd/Encoder.vcd");
$dumpvars(1,test);
inline=4'b0001;
#10
inline=4'b0010;
#10
inline = 4'b0100;
#10
inline = 4'b1000;
#10
$finish;
end
endmodule