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Enable cxxrtl blackboxes in vhdl by propagating attributes of entity #208
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This needs to be investigated: why are they kept for verilog but not for vhdl ? |
Yes, ghdl also explicitly warns that they're dropped for the entity:
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Ah ok, they indeed needs to be propagate. |
CXXRTL allows for blackboxes, that are implemented by C++ code during the simulation. To do this in Verilog, the module is marked up as follows:
I would expect a this to look akin to the following in VHDL:
but all of these attributes are discarded in the rtlil (the ones for the entity with a warning for unkept-attribute), thus not resulting in any blackbox.
This is probably related to ghdl/ghdl#2675.
Is there a way around this (by e.g. setting these attributes in yosys?) until they are propgated or a better way to write it in VHDL?
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