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Enable cxxrtl blackboxes in vhdl by propagating attributes of entity #208

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david-sawatzke opened this issue Jan 22, 2025 · 3 comments
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@david-sawatzke
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CXXRTL allows for blackboxes, that are implemented by C++ code during the simulation. To do this in Verilog, the module is marked up as follows:

(* cxxrtl_blackbox *)
module test (
(* cxxrtl_edge ="p" *) input wire clk;
input wire rst
);
// Empty

endmodule

I would expect a this to look akin to the following in VHDL:


library ieee;
use ieee.std_logic_1164.all;

entity test is
  port (
    clk_i     : in  std_ulogic;
    rstn_i    : in  std_ulogic
  );
  -- Define the custom attributes
  attribute blackbox : boolean;
  attribute blackbox of test : entity is true; -- Apply the blackbox attribute
  attribute cxxrtl_blackbox : boolean;
  attribute cxxrtl_blackbox of test : entity is true;
  attribute cxxrtl_edge : string;
  attribute cxxrtl_edge of clk_i : signal is "p"; -- Apply the edge attribute to clk_i
end test;

architecture test_rtl of test is

begin
  --black box implementation
end test_rtl;

but all of these attributes are discarded in the rtlil (the ones for the entity with a warning for unkept-attribute), thus not resulting in any blackbox.

This is probably related to ghdl/ghdl#2675.

Is there a way around this (by e.g. setting these attributes in yosys?) until they are propgated or a better way to write it in VHDL?

@tgingold
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This needs to be investigated: why are they kept for verilog but not for vhdl ?
Are they present when you write a verilog module to rtlil ?

@david-sawatzke
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david-sawatzke commented Jan 22, 2025

Yes, read_verilog has them (and since a day ago, slang povik/yosys-slang#80 as well). Since, to my understanding, if the rtlil doesn't include them, they're not there for cxxrtl, this is required.

ghdl also explicitly warns that they're dropped for the entity:

1. Executing GHDL.
test.vhd:12:15:warning: attribute "cxxrtl_blackbox" for entity "test" is not kept in the netlist [-Wunkept-attribute]
    attribute cxxrtl_blackbox of test : entity is true; -- Apply the blackbox attribute
              ^
test.vhd:14:15:warning: attribute "blackbox" for entity "test" is not kept in the netlist [-Wunkept-attribute]
    attribute blackbox of test : entity is true; -- Apply the blackbox attribute
              ^
test.vhd:16:15:warning: unhandled attribute "cxxrtl_edge" [-Wunhandled-attribute]
    attribute cxxrtl_edge of clk_i : signal is "p"; -- Apply the edge attribute to clk_i
              ^
test.vhd:14:15:warning: unhandled attribute "blackbox" [-Wunhandled-attribute]
    attribute blackbox of test : entity is true; -- Apply the blackbox attribute
              ^
test.vhd:12:15:warning: unhandled attribute "cxxrtl_blackbox" [-Wunhandled-attribute]
    attribute cxxrtl_blackbox of test : entity is true; -- Apply the blackbox attribute
              ^
Importing module test.

@tgingold
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Ah ok, they indeed needs to be propagate.
I think there is a yosys command to set attributes (as a workaround).

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