[AArch64][SVE] can improve SIMD immediate generation

[k-arrows]

Test case:

#include <arm_neon.h>

typedef short v8hi __attribute__((vector_size(16)));
typedef int v4si __attribute__((vector_size(16)));
typedef long v2di __attribute__((vector_size(16)));

v4si t1 ()
{
  return (v4si) { 0xffc, 0xffc, 0xffc, 0xffc };
}

v8hi t2 ()
{
  return (v8hi) { 510, 510, 510, 510, 510, 510, 510, 510 };
}

v2di t3 ()
{
  return (v2di) { 1, 1 };
}

When generating Advanced SIMD code, if SVE is available on target CPU, SVE move immediate can be used.
https://godbolt.org/z/9vhc6Mx1j

The same applies for SVE bitmask immediate.

Reference(GCC patches):
[AArch64: Improve SIMD immediate generation (1/3)]
[AArch64: Improve SIMD immediate generation (2/3)]
[AArch64: Add support for SIMD xor immediate (3/3)]

[llvmbot]

@llvm/issue-subscribers-backend-aarch64

Author: None (k-arrows)

Test case: ```c #include <arm_neon.h>

typedef short v8hi attribute((vector_size(16)));
typedef int v4si attribute((vector_size(16)));
typedef long v2di attribute((vector_size(16)));

v4si t1 ()
{
return (v4si) { 0xffc, 0xffc, 0xffc, 0xffc };
}

v8hi t2 ()
{
return (v8hi) { 510, 510, 510, 510, 510, 510, 510, 510 };
}

v2di t3 ()
{
return (v2di) { 1, 1 };
}

When generating Advanced SIMD code, if SVE is available on target CPU, SVE move immediate can be used.
https://godbolt.org/z/9vhc6Mx1j

The same applies for SVE bitmask immediate.

Reference(GCC patches): 
[AArch64: Improve SIMD immediate generation (1/3)]
[AArch64: Improve SIMD immediate generation (2/3)]
[AArch64: Add support for SIMD xor immediate (3/3)]
</details>