Handle ebl_cr_poweron msr

This will be needed in the future by nxdk

lib86cpu/core/instructions.cpp

@@ -1059,6 +1059,10 @@ msr_read_helper(cpu_ctx_t *cpu_ctx)
 		val = MSR_IA32_APICBASE_BSP;
 		break;
 
+	case IA32_EBL_CR_POWERON:
+		val = cpu_ctx->cpu->msr.ebl_cr_poweron;
+		break;
+
 	case IA32_BIOS_UPDT_TRIG:
 		val = 0;
 		break;
@@ -1180,6 +1184,13 @@ msr_write_helper(cpu_ctx_t *cpu_ctx)
 		}
 		break;
 
+	case IA32_EBL_CR_POWERON:
+		if (val & MSR_EBL_CR_POWERON_RES) {
+			return 1;
+		}
+		cpu_ctx->cpu->msr.ebl_cr_poweron = (cpu_ctx->cpu->msr.ebl_cr_poweron & ~MSR_EBL_CR_POWERON_RW) | (val & MSR_EBL_CR_POWERON_RW);
+		break;
+
 	case IA32_BIOS_UPDT_TRIG:
 		cpu_ctx->cpu->microcode_updated = 1;
 		break;

lib86cpu/core/internal.h

@@ -362,6 +362,7 @@ CR0_TS_MASK | CR0_EM_MASK | CR0_MP_MASK | CR0_PE_MASK)
 
 // msr register addresses
 #define IA32_APIC_BASE             0x1B
+#define IA32_EBL_CR_POWERON        0x2A
 #define IA32_BIOS_UPDT_TRIG        0x79
 #define IA32_BIOS_SIGN_ID          0x8B
 #define IA32_MTRRCAP               0xFE
@@ -401,6 +402,8 @@ CR0_TS_MASK | CR0_EM_MASK | CR0_MP_MASK | CR0_PE_MASK)
 #define MSR_MTRR_PHYSMASK_RES      0xFFFFFFF0000007FF
 #define MSR_MTRR_DEF_TYPE_RES      0xFFFFFFFFFFFFF300
 #define MSR_PAT_RES                0xF8F8F8F8F8F8F8F8
+#define MSR_EBL_CR_POWERON_RES     0xFFFFFFFFF0000821
+#define MSR_EBL_CR_POWERON_RW      0x00000000040000DE
 #define MCG_NUM_BANKS              (sizeof(msr_t::mca_banks) / sizeof(msr_t::mca_banks[0]))
 #define MCG_CTL_P                  (1 << 8)
 #define MCG_SER_P                  (1 << 24)

lib86cpu/core/registers.h

@@ -120,6 +120,7 @@ struct msr_t {
 	uint64_t mcg_status;
 	uint64_t mcg_ctl;
 	uint64_t mca_banks[10][4];
+	uint64_t ebl_cr_poweron;
 };
 
 static_assert(sizeof(uint80_t) == 10);

lib86cpu/core/translate.cpp

@@ -65,6 +65,7 @@ cpu_reset(cpu_t *cpu)
 	cpu->cpu_ctx.lazy_eflags.result = 0x100; // make zf=0
 	cpu->a20_mask = 0xFFFFFFFF; // gate closed
 	cpu->cpu_ctx.exp_info.old_exp = EXP_INVALID;
+	cpu->msr.ebl_cr_poweron = 0xC5040000; // system bus frequency = 133 MHz, clock frequency ratio = 5.5, low power mode enabled
 	cpu->msr.mcg_cap = (MCG_NUM_BANKS | MCG_CTL_P | MCG_SER_P);
 	cpu->msr.mcg_ctl = MCG_CTL_ENABLE;
 	for (unsigned i = 0; i < MCG_NUM_BANKS; ++i) {

lib86cpu/support.cpp

@@ -14,7 +14,7 @@
 #endif
 
 // This should be updated whenever cpu members that need to be saved are added/removed
-#define SAVE_STATE_ID 10
+#define SAVE_STATE_ID 11
 
 
 void