Merge pull request #2 from FlyGoat/bump

Bump to git master to get verilator working

.github/workflows/publish-to-pypi.yml

@@ -12,7 +12,7 @@ jobs:
     runs-on: ubuntu-latest
 
     steps:
-    - uses: actions/checkout@v2
+    - uses: actions/checkout@v4
       with:
         # Always clone the full depth so git-describe works.
         fetch-depth: 0
@@ -70,14 +70,14 @@ jobs:
     runs-on: ubuntu-latest
 
     steps:
-    - uses: actions/checkout@v2
+    - uses: actions/checkout@v4
       with:
         # Always clone the full depth so git-describe works.
         fetch-depth: 0
         submodules: true
 
     - name: Set up Python 🐍 ${{ matrix.python-version }}
-      uses: actions/setup-python@v2
+      uses: actions/setup-python@v5
       with:
         python-version: ${{ matrix.python-version }}
 

pythondata_cpu_mor1kx/__init__.py

@@ -4,42 +4,42 @@
 src = "https://github.com/openrisc/mor1kx.git"
 
 # Module version
-version_str = "5.1.1.post142"
-version_tuple = (5, 1, 1, 142)
+version_str = "5.2.post151"
+version_tuple = (5, 2, 151)
 try:
     from packaging.version import Version as V
-    pversion = V("5.1.1.post142")
+    pversion = V("5.2.post151")
 except ImportError:
     pass
 
 # Data version info
-data_version_str = "5.1.1.post0"
-data_version_tuple = (5, 1, 1, 0)
+data_version_str = "5.2.post3"
+data_version_tuple = (5, 2, 3)
 try:
     from packaging.version import Version as V
-    pdata_version = V("5.1.1.post0")
+    pdata_version = V("5.2.post3")
 except ImportError:
     pass
-data_git_hash = "4cebbb684bba8f9fe74f9b69e679796d4fd4a35b"
-data_git_describe = "v5.1.1-0-g4cebbb6"
+data_git_hash = "d3f15eaac6d079836d5e67b0c62d585e0e143ece"
+data_git_describe = "v5.2-3-gd3f15eaac6d0"
 data_git_msg = """\
-commit 4cebbb684bba8f9fe74f9b69e679796d4fd4a35b
-Merge: 44ea698 1a8c19b
+commit d3f15eaac6d079836d5e67b0c62d585e0e143ece
 Author: Stafford Horne <shorne@gmail.com>
-Date:   Mon May 23 06:01:28 2022 +0900
+Date:   Sun Oct 13 07:40:30 2024 +0100
 
-    Merge pull request #147 from stffrdhrn/or1k-linux-failing
+    github: Revert from ubunutu 24.04 to 22.04
     
-    Revert "dcache: Allow writing during write_pending"
+    The previous latest version skipped 2 versions in github.
+    We were running 22.04 before no 24.04.
 
 """
 
 # Tool version info
-tool_version_str = "0.0.post142"
-tool_version_tuple = (0, 0, 142)
+tool_version_str = "0.0.post148"
+tool_version_tuple = (0, 0, 148)
 try:
     from packaging.version import Version as V
-    ptool_version = V("0.0.post142")
+    ptool_version = V("0.0.post148")
 except ImportError:
     pass
 

pythondata_cpu_mor1kx/verilog/.github/workflows/ci.yml

@@ -1,10 +1,15 @@
 name: ci
 
-on: [push, pull_request, workflow_dispatch]
+on:
+  push:
+  pull_request:
+  workflow_dispatch:
+  schedule:
+    - cron: '0 1 * * *'
 
 jobs:
   verilator-lint:
-    runs-on: ubuntu-18.04
+    runs-on: ubuntu-latest
     steps:
       # Checkout Repository
       - name: Checkout
@@ -21,7 +26,7 @@ jobs:
           verilator --lint-only rtl/verilog/*.v +incdir+rtl/verilog
 
   or1k-tests:
-    runs-on: ubuntu-18.04
+    runs-on: ubuntu-22.04
     env:
       LD_LIBRARY_PATH: "/tmp/tools/lib"
       EXPECTED_FAILURES: ${{ matrix.env.EXPECTED_FAILURES }}
@@ -40,7 +45,6 @@ jobs:
           pip3 install fusesoc
           export PATH=$PATH:$HOME/.local/bin
           fusesoc --version
-          fusesoc init -y
 
       # Install Toolchain
       - name: Install Toolchain
@@ -62,6 +66,7 @@ jobs:
           git clone --depth 1 https://github.com/openrisc/or1k-tests.git -b v1.0.5
           cd or1k-tests/native
           make -j8
+          fusesoc library add fusesoc_cores https://github.com/fusesoc/fusesoc-cores
           fusesoc library add mor1kx-generic https://github.com/openrisc/mor1kx-generic.git
           fusesoc library add intgen https://github.com/openrisc/intgen.git
           fusesoc library add elf-loader https://github.com/fusesoc/elf-loader.git
@@ -88,7 +93,7 @@ jobs:
           exit $result
 
       # Upload test results
-      - uses: actions/upload-artifact@v2
+      - uses: actions/upload-artifact@v4
         if: failure()
         with:
           name: runtest-results
@@ -107,7 +112,7 @@ jobs:
           - { EXPECTED_FAILURES: "or1k-cy or1k-ext", EXTRA_CORE_ARGS: "--feature_ext NONE" }
 
   formal-verification:
-    runs-on: ubuntu-18.04
+    runs-on: ubuntu-22.04
     steps:
       #Checkout Repository
       - name: Checkout
@@ -119,7 +124,7 @@ jobs:
           sudo apt-get update
           sudo apt-get -y install g++ gperf build-essential bison flex \
             libreadline-dev gawk tcl-dev libffi-dev git graphviz xdot \
-            pkg-config python python3 libboost-system-dev \
+            pkg-config python2 python3 libboost-system-dev \
             libboost-python-dev libboost-filesystem-dev zlib1g-dev
           pip3 install dataclasses
 
@@ -133,6 +138,7 @@ jobs:
           cd formal_tools
           git clone --depth 1 https://github.com/YosysHQ/yosys.git yosys
           cd yosys
+          git submodule update --init
           make -j$(nproc)
           sudo make install
           cd ..

pythondata_cpu_mor1kx/verilog/README.md

@@ -167,21 +167,8 @@ Integration (CI) suite.  This currently covers:
 
    Status: ![Build Status](https://github.com/openrisc/mor1kx/actions/workflows/ci.yml/badge.svg)
 
-The Continous Integration suite also runs in [Librecores Jenkins](https://ci.librecores.org/)
-supported by [Librecores-CI](https://github.com/librecores/librecores-ci-jenkins-server).
-In addition regression testing, it also supports:
-
- - Yosys synthesis for monitoring resource usages.
-   [Fusesoc](https://github.com/olofk/fusesoc/blob/master/doc/icestorm.adoc)
-   provides the icestorm backend.
- - [LibreCores CI](https://github.com/librecores/docker-images/tree/master/librecores-ci)
-   Docker image provides Yosys synthesis metrics parser which outputs `Printing Statistics`.
-   Results are parsed to graphs with Performance Plugin, which can be seen at
-   [ci.librecores.org](https://ci.librecores.org/job/Projects/job/OpenRISC/job/mor1kx/)
-
-Status : [![Build Status](https://ci.librecores.org/job/Projects/job/OpenRISC/job/mor1kx/job/master/badge/icon)](https://ci.librecores.org/job/Projects/job/OpenRISC/job/mor1kx/job/master/)
-
-In the future we are working on bringing more tests including:
+We would also like to add the following tests to our continuous integration
+suite, if you would like to volunteer please reach out:
 
   - softfloat, fpu verification (may not be feasable in CI due to long run times)
   - CPU pipeline debugging verification via GDB/OpenOCD

pythondata_cpu_mor1kx/verilog/bench/formal/Makefile

@@ -21,25 +21,30 @@ TESTS := mor1kx_cache_lru \
 	mor1kx_execute_ctrl_cappuccino \
 	mor1kx_dmmu \
 	mor1kx_dcache \
-	mor1kx_lsu_cappuccino \
 	mor1kx_pcu \
 	mor1kx_pic \
 	mor1kx_ticktimer \
 	mor1kx_ctrl_cappuccino \
 	mor1kx_rf_cappuccino \
-	mor1kx_bus_if_wb32 \
-	mor1kx_wb_mux_cappuccino \
+	mor1kx_bus_if_wb32
+
+# tests that no longer work keep them here so we can easily
+# run them if we want to try and fix them.
+BROKEN_TESTS := \
+	mor1kx_lsu_cappuccino \
 	mor1kx_cpu_cappuccino \
 	mor1kx
 
-
 all: $(TESTS)
 clean:
 	rm -rf mor1kx*/
 
-.PHONY: all clean $(TESTS)
+.PHONY: all clean $(TESTS) $(BROKEN_TESTS)
 
 RTL := ../../rtl/verilog
 
+$(BROKEN_TESTS): % :
+	sby -f $@.sby
+
 $(TESTS): % :
 	sby -f $@.sby

pythondata_cpu_mor1kx/verilog/mor1kx.core

@@ -1,7 +1,7 @@
 CAPI=2:
 
-name : ::mor1kx:5.1
-#description : mor1kx - an OpenRISC processor IP core
+name : ::mor1kx:5.2
+description : mor1kx - an OpenRISC processor IP core
 
 filesets:
   core:

pythondata_cpu_mor1kx/verilog/rtl/verilog/mor1kx_cpu.v

@@ -198,13 +198,11 @@ module mor1kx_cpu
 	// synthesis translate_off
 `ifndef SYNTHESIS
    /* Provide interface hooks for register functions. */
+	`include "mor1kx_utils.vh"
+	localparam RF_ADDR_WIDTH = calc_rf_addr_width(OPTION_RF_ADDR_WIDTH,
+                                                  OPTION_RF_NUM_SHADOW_GPR);
    generate
       if (OPTION_CPU=="CAPPUCCINO") begin : monitor
-
-`include "mor1kx_utils.vh"
-         localparam RF_ADDR_WIDTH = calc_rf_addr_width(OPTION_RF_ADDR_WIDTH,
-                                                       OPTION_RF_NUM_SHADOW_GPR);
-
          function [OPTION_OPERAND_WIDTH-1:0] get_gpr;
             // verilator public
             input [RF_ADDR_WIDTH-1:0] gpr_num;