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Expanded support for CFUs.#14

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tcal-x wants to merge 34 commits intolitex-hub:masterlitex-hub/pythondata-cpu-vexriscv:masterfrom tcal-x:fomu-cfu-mm2tcal-x/pythondata-cpu-vexriscv:fomu-cfu-mm2Copy head branch name to clipboard

+60,271-209

Commits

Commits on Nov 5, 2020

• Changes to build VexRiscv versions with Cfu plugin:

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• Set up wrappers to contain the cpu+cfu.

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• Add 'clk' input to CFU modules.

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• Add perf count CSRs; rebuild CFU VexRiscv Verilogs.

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Commits on Jan 7, 2021

• Increase to 8 perf counter CSRs; rebuild.

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Commits on Jan 12, 2021

• Bump both I$, D$ from 4k to 8k.

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Commits on Feb 19, 2021

• Bump SpinalHdl/VexRiscv submodules; rebuild; widen CFU funcid port.

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Commits on Mar 5, 2021

• Delete SpinalHDL submodule.

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Commits on Mar 6, 2021

• Rebuild: VexRiscv master w/ cfu fix, Spinal 1.4.3, wide func_id.

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Commits on Apr 7, 2021

• Update CFU instr. encoding to match spec (update vex submodule too).

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• Match CFU spec; function_id now 10b {funct7,funct3}.

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Commits on Apr 8, 2021

• Remove I-format CFU instruction; it impacts timing.

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Commits on Apr 25, 2021

• Add 'SlimCfu' variants; add missing reset/rst connections.

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Commits on Apr 29, 2021

• Slim: reduce Icache size to 1kB.

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• Rebuild SlimCfu CPUs w/ 1kB Icache.

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Commits on Jun 3, 2021

• Remove wrapper mechanism for VexRiscv/CFU.

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• Rebuild Verilogs at hash e78ff1c.

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Commits on Jun 11, 2021

• Add VexRiscv for Fomu -- minimal, plus hard muldiv, plus mcycle.

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• Trim Fomu variants by removing alignment etc. checks.

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Commits on Jul 19, 2021

• Tweak the Fomu variant to remove division, debug, and writeback/memory stages.

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Commits on Jul 20, 2021

• Merge pull request #1 from JosephBushagour/jbushagour_fomu_tweaks

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Commits on Aug 2, 2021

• Require a memory and writeback stage for the CFU plugin.

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• Merge pull request #2 from JosephBushagour/fomu-cfu

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Commits on Aug 9, 2021

• Add icache, single-cycle-shift, and single-cycle multiply to the Fomu variant.

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• Merge pull request #3 from JosephBushagour/fomu-cfu

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Commits on Aug 31, 2021

• New "perf" variant has perfCSRs.

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• Rebuild affected verilogs with correct hash comment (5bb9114).

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Commits on Sep 16, 2021

• Add slimperf+cfu variant.

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Commits on Sep 21, 2021

• Merge branch 'master' into fomu-cfu-mm2

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• Rebuild Verilogs at 593e180.

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Commits on Sep 29, 2021

• Add 'slim' variant for completeness.

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Commits on Sep 30, 2021

• Rebuild VexRiscv_Slim.v so it has correct hash in comment.

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• Remove performance CSRs from 'FullCfu' variants.

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• Rebuild VexRiscv_FullCfu*.v at 7454d1a.

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