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AMDGPU: Add disjoint to or produced from lowering vector ops #122424

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Jan 10, 2025
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AMDGPU: Add disjoint to or produced from lowering vector ops #122424

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6 changes: 4 additions & 2 deletions llvm/lib/Target/AMDGPU/SIISelLowering.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -7429,7 +7429,8 @@ SDValue SITargetLowering::lowerINSERT_VECTOR_ELT(SDValue Op,
DAG.getNode(ISD::AND, SL, IntVT, DAG.getNOT(SL, BFM, IntVT), BCVec);

// 4. Get (2) and (3) ORed into the target vector.
SDValue BFI = DAG.getNode(ISD::OR, SL, IntVT, LHS, RHS);
SDValue BFI =
DAG.getNode(ISD::OR, SL, IntVT, LHS, RHS, SDNodeFlags::Disjoint);

return DAG.getNode(ISD::BITCAST, SL, VecVT, BFI);
}
Expand Down Expand Up @@ -7637,7 +7638,8 @@ SDValue SITargetLowering::lowerBUILD_VECTOR(SDValue Op,
Lo = DAG.getNode(ISD::BITCAST, SL, MVT::i16, Lo);
Lo = DAG.getNode(ISD::ZERO_EXTEND, SL, MVT::i32, Lo);

SDValue Or = DAG.getNode(ISD::OR, SL, MVT::i32, Lo, ShlHi);
SDValue Or =
DAG.getNode(ISD::OR, SL, MVT::i32, Lo, ShlHi, SDNodeFlags::Disjoint);
return DAG.getNode(ISD::BITCAST, SL, VT, Or);
}

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