Skip to content
CI

[RACL] Add RACL configuration checks #5553

Sign in to view logs

[RACL] Add RACL configuration checks

[RACL] Add RACL configuration checks #5553

Triggered via pull request February 4, 2025 17:53
@davidschrammeldavidschrammel
synchronize #26125
davidschrammel:racl-fixes-1
Status Cancelled
Total duration 15m 37s
Artifacts 1

ci.yml

on: pull_request
Lint (quick)
3m 20s
Lint (quick)
Earl Grey for CW340  /  Build bitstream
0s
Earl Grey for CW340 / Build bitstream
Earl Grey for CW310 Hyperdebug  /  Build bitstream
0s
Earl Grey for CW310 Hyperdebug / Build bitstream
Earl Grey for CW310  /  Build bitstream
0s
Earl Grey for CW310 / Build bitstream
Lint (slow)
11m 35s
Lint (slow)
Build documentation
5m 2s
Build documentation
Airgapped build
10m 10s
Airgapped build
Verible lint
1m 9s
Verible lint
Run OTBN smoke Test
2m 46s
Run OTBN smoke Test
Run OTBN crypto tests
3m 4s
Run OTBN crypto tests
Verilated English Breakfast
7m 40s
Verilated English Breakfast
Verilated Earl Grey
11m 36s
Verilated Earl Grey
CW305's Bitstream
11m 39s
CW305's Bitstream
Build Docker Containers
2m 20s
Build Docker Containers
Build and test software
10m 1s
Build and test software
QEMU smoketest
1m 56s
QEMU smoketest
CW340 Manufacturing Tests  /  FPGA test
CW340 Manufacturing Tests / FPGA test
CW340 ROM Tests  /  FPGA test
CW340 ROM Tests / FPGA test
CW340 ROM_EXT Tests  /  FPGA test
CW340 ROM_EXT Tests / FPGA test
CW340 SiVal ROM_EXT Tests  /  FPGA test
CW340 SiVal ROM_EXT Tests / FPGA test
CW340 SiVal Tests  /  FPGA test
CW340 SiVal Tests / FPGA test
CW340 Test ROM Tests  /  FPGA test
CW340 Test ROM Tests / FPGA test
CW310 Manufacturing Tests  /  FPGA test
CW310 Manufacturing Tests / FPGA test
CW310 SiVal ROM_EXT Tests  /  FPGA test
CW310 SiVal ROM_EXT Tests / FPGA test
CW310 SiVal Tests  /  FPGA test
CW310 SiVal Tests / FPGA test
Hyper310 ROM_EXT Tests  /  FPGA test
Hyper310 ROM_EXT Tests / FPGA test
CW310 ROM Tests  /  FPGA test
CW310 ROM Tests / FPGA test
CW310 Test ROM Tests  /  FPGA test
CW310 Test ROM Tests / FPGA test
Cache bitstreams to GCP
0s
Cache bitstreams to GCP
Verify FPGA jobs
0s
Verify FPGA jobs
Fit to window
Zoom out
Zoom in

Annotations

19 errors
Verilated English Breakfast
Process completed with exit code 1.
Earl Grey for CW310 / Build bitstream
Canceling since a higher priority waiting request for 'CI-refs/pull/26125/merge' exists
Earl Grey for CW310 Hyperdebug / Build bitstream
Canceling since a higher priority waiting request for 'CI-refs/pull/26125/merge' exists
Earl Grey for CW340 / Build bitstream
Canceling since a higher priority waiting request for 'CI-refs/pull/26125/merge' exists
Lint (slow)
Canceling since a higher priority waiting request for 'CI-refs/pull/26125/merge' exists
Lint (slow)
Countermeasure check failed.
Lint (slow)
Process completed with exit code 1.
Lint (slow)
The operation was canceled.
Lint (slow)
Some target names have banned characters.
Lint (slow)
Process completed with exit code 1.
Lint (slow)
Process completed with exit code 1.
Lint (slow)
Countermeasure check failed.
Lint (slow)
Process completed with exit code 1.
Verilated Earl Grey
Canceling since a higher priority waiting request for 'CI-refs/pull/26125/merge' exists
Verilated Earl Grey
The operation was canceled.
Build and test software
Canceling since a higher priority waiting request for 'CI-refs/pull/26125/merge' exists
Build and test software
The operation was canceled.
CW305's Bitstream
Canceling since a higher priority waiting request for 'CI-refs/pull/26125/merge' exists
CW305's Bitstream
The operation was canceled.

Artifacts

Produced during runtime
Name Size
verilated_englishbreakfast
7.03 MB