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[RACL] Add RACL support for mbx
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Signed-off-by: David Schrammel <davidschrammel@rivosinc.com>
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@davidschrammel
davidschrammel committed Jan 24, 2025
1 parent 30e6ff0 commit 4d0a40e
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Showing 6 changed files with 1,006 additions and 101 deletions.
32 changes: 31 additions & 1 deletion hw/ip/mbx/data/mbx.hjson
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Expand Up @@ -21,7 +21,7 @@
bus_interfaces: [
{ protocol: "tlul", direction: "device", name: "core" }
{ protocol: "tlul", direction: "host", name: "sram" }
{ protocol: "tlul", direction: "device", name: "soc" }
{ protocol: "tlul", direction: "device", name: "soc", racl_support: true }
]
inter_signal_list: [
{ struct: "logic",
Expand Down Expand Up @@ -52,6 +52,36 @@
package: "",
default: "1'b0"
}
{ struct: "racl_policy_vec",
type: "uni",
name: "racl_policies",
act: "rcv",
package: "top_racl_pkg",
desc: '''
Incoming RACL policy vector from a racl_ctrl instance.
The policy selection vector (parameter) selects the policy for each register.
'''
}
{ struct: "logic",
type: "uni",
name: "racl_error",
act: "req",
width : "1",
desc: '''
RACL error indication signal.
If 1, the error log contains valid information.
'''
}
{ struct: "racl_error_log",
type: "uni",
name: "racl_error_log",
act: "req",
width: "1"
package: "top_racl_pkg",
desc: '''
RACL error log information of this module.
'''
}
]
interrupt_list: [
{ name: "mbx_ready"
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1 change: 1 addition & 0 deletions hw/ip/mbx/mbx.core
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Expand Up @@ -10,6 +10,7 @@ filesets:
- lowrisc:prim:all
- lowrisc:tlul:headers
- lowrisc:ip:tlul
- lowrisc:systems:top_racl_pkg
files:
- rtl/mbx_reg_pkg.sv
- rtl/mbx.sv
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44 changes: 33 additions & 11 deletions hw/ip/mbx/rtl/mbx.sv
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Expand Up @@ -8,12 +8,18 @@ module mbx
import tlul_pkg::*;
import mbx_reg_pkg::*;
#(
parameter logic [NumAlerts-1:0] AlertAsyncOn = {NumAlerts{1'b1}},
parameter int unsigned CfgSramAddrWidth = 32,
parameter int unsigned CfgSramDataWidth = 32,
parameter int unsigned CfgObjectSizeWidth = 11,
parameter bit DoeIrqSupport = 1'b1,
parameter bit DoeAsyncMsgSupport = 1'b1
parameter logic [NumAlerts-1:0] AlertAsyncOn = {NumAlerts{1'b1}},
parameter int unsigned CfgSramAddrWidth = 32,
parameter int unsigned CfgSramDataWidth = 32,
parameter int unsigned CfgObjectSizeWidth = 11,
parameter bit DoeIrqSupport = 1'b1,
parameter bit DoeAsyncMsgSupport = 1'b1,
parameter bit EnableRacl = 1'b0,
parameter bit RaclErrorRsp = 1'b1,
parameter int unsigned RaclPolicySelVecCore[17] = '{17{0}},
parameter int unsigned RaclPolicySelVecSoc[4] = '{4{0}},
parameter int unsigned RaclPolicySelWinSocWDATA = 0,
parameter int unsigned RaclPolicySelWinSocRDATA = 0
) (
input logic clk_i,
input logic rst_ni,
Expand All @@ -29,6 +35,10 @@ module mbx
// Alerts
input prim_alert_pkg::alert_rx_t [NumAlerts-1:0] alert_rx_i,
output prim_alert_pkg::alert_tx_t [NumAlerts-1:0] alert_tx_o,
// RACL interface
input top_racl_pkg::racl_policy_vec_t racl_policies_i,
output logic racl_error_o,
output top_racl_pkg::racl_error_log_t racl_error_log_o,
// Device port facing OpenTitan
input tlul_pkg::tl_h2d_t core_tl_d_i,
output tlul_pkg::tl_d2h_t core_tl_d_o,
Expand Down Expand Up @@ -184,10 +194,16 @@ module mbx
assign mbx_error_set = hostif_control_error_set | imbx_overflow_error_set;

mbx_sysif #(
.CfgSramAddrWidth ( CfgSramAddrWidth ),
.CfgSramDataWidth ( CfgSramDataWidth ),
.DoeIrqSupport ( DoeIrqSupport ),
.DoeAsyncMsgSupport ( DoeAsyncMsgSupport )
.CfgSramAddrWidth ( CfgSramAddrWidth ),
.CfgSramDataWidth ( CfgSramDataWidth ),
.DoeIrqSupport ( DoeIrqSupport ),
.DoeAsyncMsgSupport ( DoeAsyncMsgSupport ),
.EnableRacl ( EnableRacl ),
.RaclErrorRsp ( RaclErrorRsp ),
.RaclPolicySelVecCore ( RaclPolicySelVecCore ),
.RaclPolicySelVecSoc ( RaclPolicySelVecSoc ),
.RaclPolicySelWinSocWDATA ( RaclPolicySelWinSocWDATA ),
.RaclPolicySelWinSocRDATA ( RaclPolicySelWinSocRDATA )
) u_sysif (
.clk_i ( clk_i ),
.rst_ni ( rst_ni ),
Expand Down Expand Up @@ -229,7 +245,11 @@ module mbx
.write_data_o ( sysif_write_data ),
.read_data_read_valid_o ( sysif_read_data_read_valid ),
.read_data_write_valid_o ( sysif_read_data_write_valid ),
.read_data_i ( sysif_read_data )
.read_data_i ( sysif_read_data ),
// RACL interface
.racl_policies_i ( racl_policies_i ),
.racl_error_o ( racl_error_o ),
.racl_error_log_o ( racl_error_o )
);


Expand Down Expand Up @@ -342,4 +362,6 @@ module mbx
`ASSERT_PRIM_REG_WE_ONEHOT_ERROR_TRIGGER_ALERT(RegWeOnehotCheck_A,
u_sysif.u_soc_regs,
alert_tx_o[0])
`ASSERT_KNOWN(RaclErrorKnown_A, racl_error_o)
`ASSERT_KNOWN(RaclErrorLogKnown_A, racl_error_log_o)
endmodule
168 changes: 95 additions & 73 deletions hw/ip/mbx/rtl/mbx_sysif.sv
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Expand Up @@ -5,54 +5,64 @@
module mbx_sysif
import tlul_pkg::*;
#(
parameter int unsigned CfgSramAddrWidth = 32,
parameter int unsigned CfgSramDataWidth = 32,
parameter int unsigned CfgSramAddrWidth = 32,
parameter int unsigned CfgSramDataWidth = 32,
// PCIe capabilities
parameter bit DoeIrqSupport = 1'b1,
parameter bit DoeAsyncMsgSupport = 1'b1
parameter bit DoeIrqSupport = 1'b1,
parameter bit DoeAsyncMsgSupport = 1'b1,
parameter bit EnableRacl = 1'b0,
parameter bit RaclErrorRsp = 1'b1,
parameter int unsigned RaclPolicySelVecCore[17] = '{17{0}},
parameter int unsigned RaclPolicySelVecSoc[4] = '{4{0}},
parameter int unsigned RaclPolicySelWinSocWDATA = 0,
parameter int unsigned RaclPolicySelWinSocRDATA = 0
) (
input logic clk_i,
input logic rst_ni,
input logic clk_i,
input logic rst_ni,
// Device port to the system fabric
input tlul_pkg::tl_h2d_t tl_sys_i,
output tlul_pkg::tl_d2h_t tl_sys_o,
output logic intg_err_o,
input tlul_pkg::tl_h2d_t tl_sys_i,
output tlul_pkg::tl_d2h_t tl_sys_o,
output logic intg_err_o,
// Custom interrupt to the system requester
output logic doe_intr_support_o,
output logic doe_intr_en_o,
output logic doe_intr_o,
output logic doe_intr_support_o,
output logic doe_intr_en_o,
output logic doe_intr_o,
// Asynchronous message to the requester
output logic doe_async_msg_support_o,
output logic doe_async_msg_en_o,
input logic doe_async_msg_set_i,
input logic doe_async_msg_clear_i,
output logic doe_async_msg_support_o,
output logic doe_async_msg_en_o,
input logic doe_async_msg_set_i,
input logic doe_async_msg_clear_i,
// Abort clearing from the host
input logic sysif_abort_ack_i,
input logic sysif_abort_ack_i,
// Access to the control register
output logic sysif_control_abort_set_o,
output logic sysif_control_go_set_o,
output logic sysif_control_abort_set_o,
output logic sysif_control_go_set_o,
// Access to the status register
input logic sysif_status_busy_valid_i,
input logic sysif_status_busy_i,
output logic sysif_status_busy_o,
input logic sysif_status_doe_intr_ready_set_i,
input logic sysif_status_error_set_i,
output logic sysif_status_error_o,
input logic sysif_status_ready_valid_i,
input logic sysif_status_ready_i,
output logic sysif_status_ready_o,
input logic sysif_status_busy_valid_i,
input logic sysif_status_busy_i,
output logic sysif_status_busy_o,
input logic sysif_status_doe_intr_ready_set_i,
input logic sysif_status_error_set_i,
output logic sysif_status_error_o,
input logic sysif_status_ready_valid_i,
input logic sysif_status_ready_i,
output logic sysif_status_ready_o,
// Alias of the interrupt address and data registers to the host interface
output logic [CfgSramAddrWidth-1:0] sysif_intr_msg_addr_o,
output logic [CfgSramDataWidth-1:0] sysif_intr_msg_data_o,
output logic [CfgSramAddrWidth-1:0] sysif_intr_msg_addr_o,
output logic [CfgSramDataWidth-1:0] sysif_intr_msg_data_o,
// Control lines for backpressuring the bus
input logic imbx_pending_i,
input logic ombx_pending_i,
input logic imbx_pending_i,
input logic ombx_pending_i,
// Data interface for inbound and outbound mailbox
output logic write_data_write_valid_o,
output logic [CfgSramDataWidth-1:0] write_data_o,
output logic read_data_read_valid_o,
output logic read_data_write_valid_o,
input logic [CfgSramDataWidth-1:0] read_data_i
output logic write_data_write_valid_o,
output logic [CfgSramDataWidth-1:0] write_data_o,
output logic read_data_read_valid_o,
output logic read_data_write_valid_o,
input logic [CfgSramDataWidth-1:0] read_data_i,
// RACL interface
input top_racl_pkg::racl_policy_vec_t racl_policies_i,
output logic racl_error_o,
output top_racl_pkg::racl_error_log_t racl_error_log_o
);
import mbx_reg_pkg::*;

Expand Down Expand Up @@ -195,53 +205,65 @@ module mbx_sysif
// the bus if there are too many outstanding requests.
logic reg_wdata_we;
logic [top_pkg::TL_DW-1:0] reg_wdata_wdata;
tlul_adapter_reg #(
.RegAw ( SocAw ),
.RegDw ( top_pkg::TL_DW ),
.EnableDataIntgGen ( 0 )
tlul_adapter_reg_racl #(
.RegAw ( SocAw ),
.RegDw ( top_pkg::TL_DW ),
.EnableDataIntgGen ( 0 ),
.EnableRacl ( EnableRacl ),
.RaclErrorRsp ( RaclErrorRsp ),
.RaclPolicySelVec ( RaclPolicySelWinSocWDATA ),
) u_wdata_reg_if (
.clk_i ( clk_i ),
.rst_ni ( rst_ni ),
.tl_i ( tl_win_h2d[MBX_WDATA_IDX] ),
.tl_o ( tl_win_d2h[MBX_WDATA_IDX] ),
.en_ifetch_i ( prim_mubi_pkg::MuBi4False ),
.intg_error_o ( ),
.we_o ( reg_wdata_we ),
.clk_i ( clk_i ),
.rst_ni ( rst_ni ),
.tl_i ( tl_win_h2d[MBX_WDATA_IDX] ),
.tl_o ( tl_win_d2h[MBX_WDATA_IDX] ),
.en_ifetch_i ( prim_mubi_pkg::MuBi4False ),
.intg_error_o ( ),
.racl_policies_i ( racl_policies_i ),
.racl_error_o ( racl_error_o ),
.racl_error_log_o ( racl_error_log_o ),
.we_o ( reg_wdata_we ),
// No Reading of the write register. Always reads zero
.re_o ( ),
.addr_o ( ),
.wdata_o ( reg_wdata_wdata ),
.be_o ( ),
.busy_i ( imbx_pending_i ),
.rdata_i ( '0 ),
.error_i ( 1'b0 )
.re_o ( ),
.addr_o ( ),
.wdata_o ( reg_wdata_wdata ),
.be_o ( ),
.busy_i ( imbx_pending_i ),
.rdata_i ( '0 ),
.error_i ( 1'b0 )
);

// Dedicated TLUL adapter for implementing the read data mailbox register via a register window.
// We use the register window to access the internal bus signals, allowing the mailbox to halt
// the bus if there are too many outstanding requests. The register is implemented as hwext
// outside of this hierarchy
tlul_adapter_reg #(
.RegAw ( SocAw ),
.RegDw ( top_pkg::TL_DW ),
.EnableDataIntgGen ( 0 )
tlul_adapter_reg_racl #(
.RegAw ( SocAw ),
.RegDw ( top_pkg::TL_DW ),
.EnableDataIntgGen ( 0 ),
.EnableRacl ( EnableRacl ),
.RaclErrorRsp ( RaclErrorRsp ),
.RaclPolicySelVec ( RaclPolicySelWinRDATA ),
) u_rdata_reg_if (
.clk_i ( clk_i ),
.rst_ni ( rst_ni ),
.tl_i ( tl_win_h2d[MBX_RDATA_IDX] ),
.tl_o ( tl_win_d2h[MBX_RDATA_IDX] ),
.en_ifetch_i ( prim_mubi_pkg::MuBi4False ),
.intg_error_o ( ),
.clk_i ( clk_i ),
.rst_ni ( rst_ni ),
.tl_i ( tl_win_h2d[MBX_RDATA_IDX] ),
.tl_o ( tl_win_d2h[MBX_RDATA_IDX] ),
.en_ifetch_i ( prim_mubi_pkg::MuBi4False ),
.intg_error_o ( ),
.racl_policies_i ( racl_policies_i ),
.racl_error_o ( racl_error_o ),
.racl_error_log_o ( racl_error_log_o ),
// No writing to the read register
.we_o ( read_data_write_valid_o ),
.re_o ( read_data_read_valid_o ),
.addr_o ( ),
.we_o ( read_data_write_valid_o ),
.re_o ( read_data_read_valid_o ),
.addr_o ( ),
// Write values are ignored. A Write simply means the read has occurred.
.wdata_o ( ),
.be_o ( ),
.busy_i ( ombx_pending_i ),
.rdata_i ( read_data_i ),
.error_i ( 1'b0 )
.wdata_o ( ),
.be_o ( ),
.busy_i ( ombx_pending_i ),
.rdata_i ( read_data_i ),
.error_i ( 1'b0 )
);

// Manual implementation of the write read mailbox register.
Expand Down
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