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[racl] Add RACL support for spi_host
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Signed-off-by: David Schrammel <davidschrammel@rivosinc.com>
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@davidschrammel
davidschrammel committed Jan 27, 2025
1 parent abb98ef commit d714af0
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Showing 12 changed files with 580 additions and 81 deletions.
32 changes: 31 additions & 1 deletion hw/ip/spi_host/data/spi_host.hjson
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Expand Up @@ -31,7 +31,7 @@
{clock: "clk_i", reset: "rst_ni", primary: true},
]
bus_interfaces: [
{ protocol: "tlul", direction: "device" }
{ protocol: "tlul", direction: "device", racl_support: true }
],
inter_signal_list: [
{ struct: "passthrough",
Expand All @@ -50,6 +50,36 @@
'''
act: "req",
}
{ struct: "racl_policy_vec",
type: "uni",
name: "racl_policies",
act: "rcv",
package: "top_racl_pkg",
desc: '''
Incoming RACL policy vector from a racl_ctrl instance.
The policy selection vector (parameter) selects the policy for each register.
'''
}
{ struct: "logic",
type: "uni",
name: "racl_error",
act: "req",
width : "1",
desc: '''
RACL error indication signal.
If 1, the error log contains valid information.
'''
}
{ struct: "racl_error_log",
type: "uni",
name: "racl_error_log",
act: "req",
width: "1"
package: "top_racl_pkg",
desc: '''
RACL error log information of this module.
'''
}
]
regwidth: "32",
param_list: [
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13 changes: 8 additions & 5 deletions hw/ip/spi_host/doc/interfaces.md
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Expand Up @@ -17,11 +17,14 @@ Referring to the [Comportable guideline for peripheral device functionality](htt

## [Inter-Module Signals](https://opentitan.org/book/doc/contributing/hw/comportability/index.html#inter-signal-handling)

| Port Name | Package::Struct | Type | Act | Width | Description |
|:-------------|:----------------------------|:--------|:------|--------:|:-----------------------------------------------------------------------------------------------------------------------------------------------|
| passthrough | spi_device_pkg::passthrough | req_rsp | rsp | 1 | |
| lsio_trigger | logic | uni | req | 1 | Self-clearing status trigger for the DMA. Set when RX or TX FIFOs are past their configured watermarks matching watermark interrupt behaviour. |
| tl | tlul_pkg::tl | req_rsp | rsp | 1 | |
| Port Name | Package::Struct | Type | Act | Width | Description |
|:---------------|:------------------------------|:--------|:------|--------:|:-----------------------------------------------------------------------------------------------------------------------------------------------|
| passthrough | spi_device_pkg::passthrough | req_rsp | rsp | 1 | |
| lsio_trigger | logic | uni | req | 1 | Self-clearing status trigger for the DMA. Set when RX or TX FIFOs are past their configured watermarks matching watermark interrupt behaviour. |
| racl_policies | top_racl_pkg::racl_policy_vec | uni | rcv | 1 | Incoming RACL policy vector from a racl_ctrl instance. The policy selection vector (parameter) selects the policy for each register. |
| racl_error | logic | uni | req | 1 | RACL error indication signal. If 1, the error log contains valid information. |
| racl_error_log | top_racl_pkg::racl_error_log | uni | req | 1 | RACL error log information of this module. |
| tl | tlul_pkg::tl | req_rsp | rsp | 1 | |

## Interrupts

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72 changes: 54 additions & 18 deletions hw/ip/spi_host/rtl/spi_host.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -11,8 +11,13 @@
module spi_host
import spi_host_reg_pkg::*;
#(
parameter logic [NumAlerts-1:0] AlertAsyncOn = {NumAlerts{1'b1}},
parameter int unsigned NumCS = 1
parameter logic [NumAlerts-1:0] AlertAsyncOn = {NumAlerts{1'b1}},
parameter int unsigned NumCS = 1,
parameter bit EnableRacl = 1'b0,
parameter bit RaclErrorRsp = 1'b1,
parameter int unsigned RaclPolicySelVec[12] = '{12{0}},
parameter int unsigned RaclPolicySelWinRXDATA = 0,
parameter int unsigned RaclPolicySelWinTXDATA = 0
) (
input clk_i,
input rst_ni,
Expand All @@ -25,6 +30,11 @@ module spi_host
input prim_alert_pkg::alert_rx_t [NumAlerts-1:0] alert_rx_i,
output prim_alert_pkg::alert_tx_t [NumAlerts-1:0] alert_tx_o,

// RACL interface
input top_racl_pkg::racl_policy_vec_t racl_policies_i,
output logic racl_error_o,
output top_racl_pkg::racl_error_log_t racl_error_log_o,

// SPI Interface
output logic cio_sck_o,
output logic cio_sck_en_o,
Expand All @@ -51,22 +61,37 @@ module spi_host
spi_host_reg2hw_t reg2hw;
spi_host_hw2reg_t hw2reg;

logic racl_error_regs;
logic racl_error_window;
top_racl_pkg::racl_error_log_t racl_error_regs_log;
top_racl_pkg::racl_error_log_t racl_error_window_log;
// We are combining all racl errors here because only one of them can be set at any time.
assign racl_error_o = racl_error_regs | racl_error_window;
assign racl_error_log_o = racl_error_regs_log | racl_error_window_log;

tlul_pkg::tl_h2d_t fifo_win_h2d [2];
tlul_pkg::tl_d2h_t fifo_win_d2h [2];

// Register module
logic [NumAlerts-1:0] alert_test, alerts;
spi_host_reg_top u_reg (
spi_host_reg_top #(
.EnableRacl ( EnableRacl ),
.RaclErrorRsp ( RaclErrorRsp ),
.RaclPolicySelVec ( RaclPolicySelVec )
) u_reg (
.clk_i,
.rst_ni,
.tl_i (tl_i),
.tl_o (tl_o),
.tl_win_o (fifo_win_h2d),
.tl_win_i (fifo_win_d2h),
.tl_i ( tl_i ),
.tl_o ( tl_o ),
.tl_win_o ( fifo_win_h2d ),
.tl_win_i ( fifo_win_d2h ),
.reg2hw,
.hw2reg,
// SEC_CM: BUS.INTEGRITY
.intg_err_o (alerts[0])
.intg_err_o ( alerts[0] ),
.racl_policies_i ( racl_policies_i ),
.racl_error_o ( racl_error_regs ),
.racl_error_log_o ( racl_error_regs_log )
);

// Alerts
Expand Down Expand Up @@ -293,18 +318,26 @@ module spi_host
logic rx_valid;
logic rx_ready;

spi_host_window u_window (
spi_host_window #(
.EnableRacl ( EnableRacl ),
.RaclErrorRsp ( RaclErrorRsp ),
.RaclPolicySelWinRXDATA ( RaclPolicySelWinRXDATA ),
.RaclPolicySelWinTXDATA ( RaclPolicySelWinTXDATA )
) u_window (
.clk_i,
.rst_ni,
.rx_win_i (fifo_win_h2d[0]),
.rx_win_o (fifo_win_d2h[0]),
.tx_win_i (fifo_win_h2d[1]),
.tx_win_o (fifo_win_d2h[1]),
.tx_data_o (tx_data),
.tx_be_o (tx_be),
.tx_valid_o (tx_valid),
.rx_data_i (rx_data),
.rx_ready_o (rx_ready)
.rx_win_i ( fifo_win_h2d[0] ),
.rx_win_o ( fifo_win_d2h[0] ),
.tx_win_i ( fifo_win_h2d[1] ),
.tx_win_o ( fifo_win_d2h[1] ),
.tx_data_o ( tx_data ),
.tx_be_o ( tx_be ),
.tx_valid_o ( tx_valid ),
.rx_data_i ( rx_data ),
.rx_ready_o ( rx_ready ),
.racl_policies_i ( racl_policies_i ),
.racl_error_o ( racl_error_window ),
.racl_error_log_o ( racl_error_window_log )
);

logic [31:0] core_tx_data;
Expand Down Expand Up @@ -603,6 +636,9 @@ module spi_host
`ASSERT_KNOWN(IntrSpiEventKnownO_A, intr_spi_event_o)
`ASSERT_KNOWN(IntrErrorKnownO_A, intr_error_o)
`ASSERT_KNOWN(LsioTriggerKnown_A, lsio_trigger_o)
`ASSERT_KNOWN(RaclErrorKnown_A, racl_error_o)
`ASSERT_KNOWN(RaclErrorLogKnown_A, racl_error_log_o)


// passthrough_o.s is passed through to spi_device, it may contain unknown data,
// but the unknown data won't be used based on the SPI protocol.
Expand Down
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