[hw,sram_ctrl,rtl] Add flop stage on RAM output

This PR adds support for an optional flop stage on the RAM macro output. The support for this stage is already present but this PR adds the necesary parameters to sram_ctrl to be able to configure it. For Darjeeling, this flop stage is enabled on all sram_ctrl isntances. For the other tops it remains disabled. Signed-off-by: Robert Schilling <rschilling@rivosinc.com>
lowRISC · Jan 21, 2025 · e1d18e5 · e1d18e5
1 parent 3683c71
commit e1d18e5
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Showing 10 changed files with 95 additions and 11 deletions.
diff --git a/hw/ip/prim/rtl/prim_ram_1p_scr.sv b/hw/ip/prim/rtl/prim_ram_1p_scr.sv
@@ -49,6 +49,8 @@ module prim_ram_1p_scr import prim_ram_1p_pkg::*; #(
   // If set to 0, the cipher primitive is replicated, and together with a wider nonce input,
   // a unique keystream is generated for the full data width.
   parameter  bit ReplicateKeyStream  = 1'b0,
+  // Add a flop stage on the RAM macro output
+  parameter bit FlopRamOutput        = 0,
   // Derived parameters
   localparam int AddrWidth           = prim_util_pkg::vbits(Depth),
   // Depending on the data width, we need to instantiate multiple parallel cipher primitives to
@@ -492,7 +494,7 @@ module prim_ram_1p_scr import prim_ram_1p_pkg::*; #(
     .EnableECC(1'b0),
     .EnableParity(EnableParity),
     .EnableInputPipeline(1'b0),
-    .EnableOutputPipeline(1'b0)
+    .EnableOutputPipeline(FlopRamOutput)
   ) u_prim_ram_1p_adv (
     .clk_i,
     .rst_ni,

diff --git a/hw/ip/sram_ctrl/data/sram_ctrl.hjson b/hw/ip/sram_ctrl/data/sram_ctrl.hjson
@@ -107,6 +107,13 @@
       expose:    "true",
       default:   "3"
     },
+    { name:      "FlopRamOutput",
+      desc:      "Add a flop stage on the RAM macro output",
+      type:      "bit",
+      local:     "false",
+      expose:    "true",
+      default:   "0"
+    },
   ]
 
   features: [

diff --git a/hw/ip/sram_ctrl/rtl/sram_ctrl.sv b/hw/ip/sram_ctrl/rtl/sram_ctrl.sv
@@ -24,6 +24,8 @@ module sram_ctrl
   // PRINCE has 5 half rounds in its original form, which corresponds to 2*5 + 1 effective rounds.
   // Setting this to 3 lowers this to approximately 7 effective rounds.
   parameter int NumPrinceRoundsHalf                     = 3,
+  // Add a flop stage on the RAM macro output
+  parameter bit FlopRamOutput                           = 0,
   // Random netlist constants
   parameter  otp_ctrl_pkg::sram_key_t   RndCnstSramKey   = RndCnstSramKeyDefault,
   parameter  otp_ctrl_pkg::sram_nonce_t RndCnstSramNonce = RndCnstSramNonceDefault,
@@ -550,7 +552,8 @@ module sram_ctrl
     .InstDepth(InstDepth),
     .EnableParity(0),
     .DataBitsPerMask(DataWidth),
-    .NumPrinceRoundsHalf(NumPrinceRoundsHalf)
+    .NumPrinceRoundsHalf(NumPrinceRoundsHalf),
+    .FlopRamOutput(FlopRamOutput)
   ) u_prim_ram_1p_scr (
     .clk_i,
     .rst_ni,

diff --git a/hw/top_darjeeling/data/autogen/top_darjeeling.gen.hjson b/hw/top_darjeeling/data/autogen/top_darjeeling.gen.hjson
@@ -4060,6 +4060,7 @@
       {
         InstrExec: "0"
         InstSize: 4096
+        FlopRamOutput: 1
       }
       base_addrs:
       {
@@ -4174,6 +4175,15 @@
           expose: "true"
           name_top: SramCtrlRetAonNumPrinceRoundsHalf
         }
+        {
+          name: FlopRamOutput
+          desc: Add a flop stage on the RAM macro output
+          type: bit
+          default: 1
+          local: "false"
+          expose: "true"
+          name_top: SramCtrlRetAonFlopRamOutput
+        }
       ]
       inter_signal_list:
       [
@@ -6299,6 +6309,7 @@
       {
         InstrExec: "1"
         InstSize: 65536
+        FlopRamOutput: 1
       }
       base_addrs:
       {
@@ -6417,6 +6428,15 @@
           expose: "true"
           name_top: SramCtrlMainNumPrinceRoundsHalf
         }
+        {
+          name: FlopRamOutput
+          desc: Add a flop stage on the RAM macro output
+          type: bit
+          default: 1
+          local: "false"
+          expose: "true"
+          name_top: SramCtrlMainFlopRamOutput
+        }
       ]
       inter_signal_list:
       [
@@ -6571,6 +6591,7 @@
       {
         InstrExec: "0"
         InstSize: 4096
+        FlopRamOutput: 1
       }
       base_addrs:
       {
@@ -6689,6 +6710,15 @@
           expose: "true"
           name_top: SramCtrlMboxNumPrinceRoundsHalf
         }
+        {
+          name: FlopRamOutput
+          desc: Add a flop stage on the RAM macro output
+          type: bit
+          default: 1
+          local: "false"
+          expose: "true"
+          name_top: SramCtrlMboxFlopRamOutput
+        }
       ]
       inter_signal_list:
       [

diff --git a/hw/top_darjeeling/data/top_darjeeling.hjson b/hw/top_darjeeling/data/top_darjeeling.hjson
@@ -616,7 +616,8 @@
       domain: ["Aon"],
       param_decl: {
         InstrExec: "0",
-        InstSize: 4096
+        InstSize: 4096,
+        FlopRamOutput: 1
       }
       base_addrs: {
         regs: {hart: "0x30500000"},
@@ -769,7 +770,8 @@
       // later be permanently disabled using the EN_SRAM_IFETCH switch in OTP.
       param_decl: {
         InstrExec: "1",
-        InstSize: 65536
+        InstSize: 65536,
+        FlopRamOutput: 1
       }
       base_addrs: {
         regs: {hart: "0x211c0000"},
@@ -795,7 +797,8 @@
       reset_connections: {rst_ni: "lc", rst_otp_ni: "lc_io_div4"},
       param_decl: {
         InstrExec: "0",
-        InstSize: 4096
+        InstSize: 4096,
+        FlopRamOutput: 1
       }
       base_addrs: {
         regs: {hart: "0x211d0000"},

diff --git a/hw/top_darjeeling/rtl/autogen/top_darjeeling.sv b/hw/top_darjeeling/rtl/autogen/top_darjeeling.sv
@@ -51,6 +51,7 @@ module top_darjeeling #(
   parameter int SramCtrlRetAonNumRamInst = 1,
   parameter bit SramCtrlRetAonInstrExec = 0,
   parameter int SramCtrlRetAonNumPrinceRoundsHalf = 3,
+  parameter bit SramCtrlRetAonFlopRamOutput = 1,
   // parameters for rv_dm
   parameter logic [31:0] RvDmIdcodeValue = 32'h 0000_0001,
   parameter bit RvDmUseDmiInterface = 1,
@@ -90,11 +91,13 @@ module top_darjeeling #(
   parameter int SramCtrlMainNumRamInst = 1,
   parameter bit SramCtrlMainInstrExec = 1,
   parameter int SramCtrlMainNumPrinceRoundsHalf = 3,
+  parameter bit SramCtrlMainFlopRamOutput = 1,
   // parameters for sram_ctrl_mbox
   parameter int SramCtrlMboxInstSize = 4096,
   parameter int SramCtrlMboxNumRamInst = 1,
   parameter bit SramCtrlMboxInstrExec = 0,
   parameter int SramCtrlMboxNumPrinceRoundsHalf = 3,
+  parameter bit SramCtrlMboxFlopRamOutput = 1,
   // parameters for rom_ctrl0
   parameter RomCtrl0BootRomInitFile = "",
   parameter bit SecRomCtrl0DisableScrambling = 1'b0,
@@ -1677,7 +1680,8 @@ module top_darjeeling #(
     .InstSize(SramCtrlRetAonInstSize),
     .NumRamInst(SramCtrlRetAonNumRamInst),
     .InstrExec(SramCtrlRetAonInstrExec),
-    .NumPrinceRoundsHalf(SramCtrlRetAonNumPrinceRoundsHalf)
+    .NumPrinceRoundsHalf(SramCtrlRetAonNumPrinceRoundsHalf),
+    .FlopRamOutput(SramCtrlRetAonFlopRamOutput)
   ) u_sram_ctrl_ret_aon (
       // [52]: fatal_error
       .alert_tx_o  ( alert_tx[52:52] ),
@@ -2044,7 +2048,8 @@ module top_darjeeling #(
     .InstSize(SramCtrlMainInstSize),
     .NumRamInst(SramCtrlMainNumRamInst),
     .InstrExec(SramCtrlMainInstrExec),
-    .NumPrinceRoundsHalf(SramCtrlMainNumPrinceRoundsHalf)
+    .NumPrinceRoundsHalf(SramCtrlMainNumPrinceRoundsHalf),
+    .FlopRamOutput(SramCtrlMainFlopRamOutput)
   ) u_sram_ctrl_main (
       // [70]: fatal_error
       .alert_tx_o  ( alert_tx[70:70] ),
@@ -2079,7 +2084,8 @@ module top_darjeeling #(
     .InstSize(SramCtrlMboxInstSize),
     .NumRamInst(SramCtrlMboxNumRamInst),
     .InstrExec(SramCtrlMboxInstrExec),
-    .NumPrinceRoundsHalf(SramCtrlMboxNumPrinceRoundsHalf)
+    .NumPrinceRoundsHalf(SramCtrlMboxNumPrinceRoundsHalf),
+    .FlopRamOutput(SramCtrlMboxFlopRamOutput)
   ) u_sram_ctrl_mbox (
       // [71]: fatal_error
       .alert_tx_o  ( alert_tx[71:71] ),

diff --git a/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson b/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson
@@ -5332,6 +5332,15 @@
           expose: "true"
           name_top: SramCtrlRetAonNumPrinceRoundsHalf
         }
+        {
+          name: FlopRamOutput
+          desc: Add a flop stage on the RAM macro output
+          type: bit
+          default: "0"
+          local: "false"
+          expose: "true"
+          name_top: SramCtrlRetAonFlopRamOutput
+        }
       ]
       inter_signal_list:
       [
@@ -8231,6 +8240,15 @@
           expose: "true"
           name_top: SramCtrlMainNumPrinceRoundsHalf
         }
+        {
+          name: FlopRamOutput
+          desc: Add a flop stage on the RAM macro output
+          type: bit
+          default: "0"
+          local: "false"
+          expose: "true"
+          name_top: SramCtrlMainFlopRamOutput
+        }
       ]
       inter_signal_list:
       [

diff --git a/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv b/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv
@@ -64,6 +64,7 @@ module top_earlgrey #(
   parameter int SramCtrlRetAonNumRamInst = 1,
   parameter bit SramCtrlRetAonInstrExec = 0,
   parameter int SramCtrlRetAonNumPrinceRoundsHalf = 3,
+  parameter bit SramCtrlRetAonFlopRamOutput = 0,
   // parameters for flash_ctrl
   parameter bit SecFlashCtrlScrambleEn = 1,
   parameter int FlashCtrlProgFifoDepth = 4,
@@ -109,6 +110,7 @@ module top_earlgrey #(
   parameter int SramCtrlMainNumRamInst = 1,
   parameter bit SramCtrlMainInstrExec = 1,
   parameter int SramCtrlMainNumPrinceRoundsHalf = 2,
+  parameter bit SramCtrlMainFlopRamOutput = 0,
   // parameters for rom_ctrl
   parameter RomCtrlBootRomInitFile = "",
   parameter bit SecRomCtrlDisableScrambling = 1'b0,
@@ -2134,7 +2136,8 @@ module top_earlgrey #(
     .InstSize(SramCtrlRetAonInstSize),
     .NumRamInst(SramCtrlRetAonNumRamInst),
     .InstrExec(SramCtrlRetAonInstrExec),
-    .NumPrinceRoundsHalf(SramCtrlRetAonNumPrinceRoundsHalf)
+    .NumPrinceRoundsHalf(SramCtrlRetAonNumPrinceRoundsHalf),
+    .FlopRamOutput(SramCtrlRetAonFlopRamOutput)
   ) u_sram_ctrl_ret_aon (
       // [34]: fatal_error
       .alert_tx_o  ( alert_tx[34:34] ),
@@ -2618,7 +2621,8 @@ module top_earlgrey #(
     .InstSize(SramCtrlMainInstSize),
     .NumRamInst(SramCtrlMainNumRamInst),
     .InstrExec(SramCtrlMainInstrExec),
-    .NumPrinceRoundsHalf(SramCtrlMainNumPrinceRoundsHalf)
+    .NumPrinceRoundsHalf(SramCtrlMainNumPrinceRoundsHalf),
+    .FlopRamOutput(SramCtrlMainFlopRamOutput)
   ) u_sram_ctrl_main (
       // [59]: fatal_error
       .alert_tx_o  ( alert_tx[59:59] ),

diff --git a/hw/top_englishbreakfast/data/autogen/top_englishbreakfast.gen.hjson b/hw/top_englishbreakfast/data/autogen/top_englishbreakfast.gen.hjson
@@ -3645,6 +3645,15 @@
           expose: "true"
           name_top: SramCtrlMainNumPrinceRoundsHalf
         }
+        {
+          name: FlopRamOutput
+          desc: Add a flop stage on the RAM macro output
+          type: bit
+          default: "0"
+          local: "false"
+          expose: "true"
+          name_top: SramCtrlMainFlopRamOutput
+        }
       ]
       inter_signal_list:
       [

diff --git a/hw/top_englishbreakfast/rtl/autogen/top_englishbreakfast.sv b/hw/top_englishbreakfast/rtl/autogen/top_englishbreakfast.sv
@@ -51,6 +51,7 @@ module top_englishbreakfast #(
   parameter int SramCtrlMainNumRamInst = 1,
   parameter bit SramCtrlMainInstrExec = 1,
   parameter int SramCtrlMainNumPrinceRoundsHalf = 3,
+  parameter bit SramCtrlMainFlopRamOutput = 0,
   // parameters for rom_ctrl
   parameter RomCtrlBootRomInitFile = "",
   parameter bit SecRomCtrlDisableScrambling = 1'b1,
@@ -1177,7 +1178,8 @@ module top_englishbreakfast #(
     .InstSize(SramCtrlMainInstSize),
     .NumRamInst(SramCtrlMainNumRamInst),
     .InstrExec(SramCtrlMainInstrExec),
-    .NumPrinceRoundsHalf(SramCtrlMainNumPrinceRoundsHalf)
+    .NumPrinceRoundsHalf(SramCtrlMainNumPrinceRoundsHalf),
+    .FlopRamOutput(SramCtrlMainFlopRamOutput)
   ) u_sram_ctrl_main (
       // [22]: fatal_error
       .alert_tx_o  ( alert_tx[22:22] ),