cvm: Refactor ohcl/ovmm emulator for flexible register retrieval and update

openhcl/virt_mshv_vtl/src/processor/hardware_cvm/mod.rs

@@ -1311,7 +1311,9 @@ pub(crate) fn validate_xsetbv_exit(input: XsetbvExitInput) -> Option<u64> {
     Some(xfem)
 }
 
-impl<T: CpuIo, B: HardwareIsolatedBacking> TranslateGvaSupport for UhEmulationState<'_, '_, T, B> {
+impl<'a, 'b, T: CpuIo, B: HardwareIsolatedBacking> TranslateGvaSupport
+    for UhEmulationState<'a, 'b, T, B>
+{
     type Error = UhRunVpError;
 
     fn guest_memory(&self) -> &GuestMemory {

openhcl/virt_mshv_vtl/src/processor/mod.rs

@@ -68,6 +68,7 @@ use virt::Processor;
 use virt::StopVp;
 use virt::VpHaltReason;
 use virt::VpIndex;
+use virt_support_x86emu::emulate::EmulatorSupport;
 use vm_topology::processor::TargetVpInfo;
 use vmcore::vmtime::VmTimeAccess;
 use vtl_array::VtlArray;
@@ -1025,6 +1026,38 @@ impl<'a, T: Backing> UhProcessor<'a, T> {
         Ok(v)
     }
 
+    /// Emulates an instruction due to a single-bit monitor page write
+    #[cfg(guest_arch = "x86_64")]
+    fn emulate_fast_path<D: CpuIo>(
+        &mut self,
+        tlb_lock_held: bool,
+        devices: &D,
+        interruption_pending: bool,
+        vtl: GuestVtl,
+    ) -> Option<u32>
+    where
+        for<'b> UhEmulationState<'b, 'a, D, T>: EmulatorSupport<Error = UhRunVpError>,
+    {
+        let guest_memory = &self.partition.gm[vtl];
+        let mut emulation_state = UhEmulationState {
+            vp: &mut *self,
+            interruption_pending,
+            devices,
+            vtl,
+            cache: T::EmulationCache::default(),
+        };
+        emulation_state.load_registers();
+        let res = virt_support_x86emu::emulate::emulate_mnf_write_fast_path(
+            &mut emulation_state,
+            guest_memory,
+            devices,
+            interruption_pending,
+            tlb_lock_held,
+        );
+        emulation_state.flush();
+        res
+    }
+
     /// Emulates an instruction due to a memory access exit.
     #[cfg(guest_arch = "x86_64")]
     async fn emulate<D: CpuIo>(
@@ -1034,22 +1067,22 @@ impl<'a, T: Backing> UhProcessor<'a, T> {
         vtl: GuestVtl,
     ) -> Result<(), VpHaltReason<UhRunVpError>>
     where
-        for<'b> UhEmulationState<'b, 'a, D, T>:
-            virt_support_x86emu::emulate::EmulatorSupport<Error = UhRunVpError>,
+        for<'b> UhEmulationState<'b, 'a, D, T>: EmulatorSupport<Error = UhRunVpError>,
     {
         let guest_memory = &self.partition.gm[vtl];
-        virt_support_x86emu::emulate::emulate(
-            &mut UhEmulationState {
-                vp: &mut *self,
-                interruption_pending,
-                devices,
-                vtl,
-                cache: T::EmulationCache::default(),
-            },
-            guest_memory,
+        let mut emulation_state = UhEmulationState {
+            vp: &mut *self,
+            interruption_pending,
             devices,
-        )
-        .await
+            vtl,
+            cache: T::EmulationCache::default(),
+        };
+        emulation_state.load_registers();
+        let res =
+            virt_support_x86emu::emulate::emulate(&mut emulation_state, guest_memory, devices)
+                .await;
+        emulation_state.flush();
+        res
     }
 
     /// Emulates an instruction due to a memory access exit.
@@ -1174,10 +1207,6 @@ struct UhEmulationState<'a, 'b, T: CpuIo, U: Backing> {
     interruption_pending: bool,
     devices: &'a T,
     vtl: GuestVtl,
-    #[cfg_attr(
-        guest_arch = "x86_64",
-        expect(dead_code, reason = "not used yet in x86_64")
-    )]
     cache: U::EmulationCache,
 }
 

openhcl/virt_mshv_vtl/src/processor/mshv/x64.rs

@@ -84,6 +84,7 @@ use x86defs::xsave::XsaveHeader;
 use x86defs::xsave::XFEATURE_SSE;
 use x86defs::xsave::XFEATURE_X87;
 use x86defs::RFlags;
+use x86defs::SegmentRegister;
 use zerocopy::AsBytes;
 use zerocopy::FromBytes;
 use zerocopy::FromZeroes;
@@ -125,7 +126,7 @@ struct ProcessorStatsX86 {
 impl BackingPrivate for HypervisorBackedX86 {
     type HclBacking = MshvX64;
     type Shared = ();
-    type EmulationCache = ();
+    type EmulationCache = x86emu::CpuState;
 
     fn shared(_: &BackingShared) -> &Self::Shared {
         &()
@@ -704,18 +705,14 @@ impl<'a, 'b> InterceptHandler<'a, 'b> {
             == self.vp.partition.monitor_page.gpa()
             && message.header.intercept_access_type == HvInterceptAccessType::WRITE
         {
-            let instruction_bytes = message.instruction_bytes;
-            let instruction_bytes = &instruction_bytes[..message.instruction_byte_count as usize];
             let tlb_lock_held = message.memory_access_info.gva_gpa_valid()
                 || message.memory_access_info.tlb_locked();
-            let mut state = self.vp.emulator_state(self.intercepted_vtl);
-            if let Some(bit) = virt_support_x86emu::emulate::emulate_mnf_write_fast_path(
-                instruction_bytes,
-                &mut state,
-                interruption_pending,
+            if let Some(bit) = self.vp.emulate_fast_path(
                 tlb_lock_held,
+                dev,
+                interruption_pending,
+                self.intercepted_vtl,
             ) {
-                self.vp.set_emulator_state(self.intercepted_vtl, &state);
                 if let Some(connection_id) = self.vp.partition.monitor_page.write_bit(bit) {
                     signal_mnf(dev, connection_id);
                 }
@@ -1141,62 +1138,6 @@ impl UhProcessor<'_, HypervisorBackedX86> {
             .expect("set_vp_register should succeed for pending event");
     }
 
-    fn emulator_state(&mut self, vtl: GuestVtl) -> x86emu::CpuState {
-        const NAMES: &[HvX64RegisterName] = &[
-            HvX64RegisterName::Rsp,
-            HvX64RegisterName::Es,
-            HvX64RegisterName::Ds,
-            HvX64RegisterName::Fs,
-            HvX64RegisterName::Gs,
-            HvX64RegisterName::Ss,
-            HvX64RegisterName::Cr0,
-            HvX64RegisterName::Efer,
-        ];
-        let mut values = [FromZeroes::new_zeroed(); NAMES.len()];
-        self.runner
-            .get_vp_registers(vtl, NAMES, &mut values)
-            .expect("register query should not fail");
-
-        let [rsp, es, ds, fs, gs, ss, cr0, efer] = values;
-
-        let mut gps = self.runner.cpu_context().gps;
-        gps[x86emu::CpuState::RSP] = rsp.as_u64();
-
-        let message = self.runner.exit_message();
-        let header = HvX64InterceptMessageHeader::ref_from_prefix(message.payload()).unwrap();
-
-        x86emu::CpuState {
-            gps,
-            segs: [
-                from_seg(es.into()),
-                from_seg(header.cs_segment),
-                from_seg(ss.into()),
-                from_seg(ds.into()),
-                from_seg(fs.into()),
-                from_seg(gs.into()),
-            ],
-            rip: header.rip,
-            rflags: header.rflags.into(),
-            cr0: cr0.as_u64(),
-            efer: efer.as_u64(),
-        }
-    }
-
-    fn set_emulator_state(&mut self, vtl: GuestVtl, state: &x86emu::CpuState) {
-        self.runner
-            .set_vp_registers(
-                vtl,
-                [
-                    (HvX64RegisterName::Rip, state.rip),
-                    (HvX64RegisterName::Rflags, state.rflags.into()),
-                    (HvX64RegisterName::Rsp, state.gps[x86emu::CpuState::RSP]),
-                ],
-            )
-            .unwrap();
-
-        self.runner.cpu_context_mut().gps = state.gps;
-    }
-
     fn set_vsm_partition_config(
         &mut self,
         vtl: GuestVtl,
@@ -1306,6 +1247,67 @@ impl UhProcessor<'_, HypervisorBackedX86> {
 impl<T: CpuIo> EmulatorSupport for UhEmulationState<'_, '_, T, HypervisorBackedX86> {
     type Error = UhRunVpError;
 
+    fn load_registers(&mut self) {
+        const NAMES: &[HvX64RegisterName] = &[
+            HvX64RegisterName::Rsp,
+            HvX64RegisterName::Es,
+            HvX64RegisterName::Ds,
+            HvX64RegisterName::Fs,
+            HvX64RegisterName::Gs,
+            HvX64RegisterName::Ss,
+            HvX64RegisterName::Cr0,
+            HvX64RegisterName::Efer,
+        ];
+        let mut values = [FromZeroes::new_zeroed(); NAMES.len()];
+        self.vp
+            .runner
+            .get_vp_registers(self.vtl, NAMES, &mut values)
+            .expect("register query should not fail");
+
+        let [rsp, es, ds, fs, gs, ss, cr0, efer] = values;
+
+        let mut gps = self.vp.runner.cpu_context().gps;
+        gps[x86emu::CpuState::RSP] = rsp.as_u64();
+
+        let message = self.vp.runner.exit_message();
+        let header = HvX64InterceptMessageHeader::ref_from_prefix(message.payload()).unwrap();
+
+        self.cache = x86emu::CpuState {
+            gps,
+            segs: [
+                from_seg(es.into()),
+                from_seg(header.cs_segment),
+                from_seg(ss.into()),
+                from_seg(ds.into()),
+                from_seg(fs.into()),
+                from_seg(gs.into()),
+            ],
+            rip: header.rip,
+            rflags: header.rflags.into(),
+            cr0: cr0.as_u64(),
+            efer: efer.as_u64(),
+        };
+    }
+
+    fn flush(&mut self) {
+        self.vp
+            .runner
+            .set_vp_registers(
+                self.vtl,
+                [
+                    (HvX64RegisterName::Rip, self.cache.rip),
+                    (HvX64RegisterName::Rflags, self.cache.rflags.into()),
+                    (
+                        HvX64RegisterName::Rsp,
+                        self.cache.gps[x86emu::CpuState::RSP],
+                    ),
+                ],
+            )
+            .unwrap();
+
+        self.vp.runner.cpu_context_mut().gps = self.cache.gps;
+    }
+
     fn vp_index(&self) -> VpIndex {
         self.vp.vp_index()
     }
@@ -1314,15 +1316,55 @@ impl<T: CpuIo> EmulatorSupport for UhEmulationState<'_, '_, T, HypervisorBackedX
         self.vp.partition.caps.vendor
     }
 
-    fn state(&mut self) -> Result<x86emu::CpuState, Self::Error> {
-        Ok(self.vp.emulator_state(self.vtl))
+    fn gp_sign_extend(&mut self, reg: usize) -> i64 {
+        self.gp(reg) as i64
+    }
+
+    fn gp(&mut self, reg: usize) -> u64 {
+        self.cache.gps[reg]
+    }
+
+    fn set_gp(&mut self, reg: usize, v: u64) {
+        self.cache.gps[reg] = v;
+    }
+
+    fn xmm(&mut self, index: usize) -> u128 {
+        u128::from_le_bytes(self.vp.runner.cpu_context().fx_state.xmm[index])
     }
 
-    fn set_state(&mut self, state: x86emu::CpuState) -> Result<(), Self::Error> {
-        self.vp.set_emulator_state(self.vtl, &state);
+    fn set_xmm(&mut self, index: usize, v: u128) -> Result<(), Self::Error> {
+        self.vp.runner.cpu_context_mut().fx_state.xmm[index] = v.to_le_bytes();
         Ok(())
     }
 
+    fn rip(&mut self) -> u64 {
+        self.cache.rip
+    }
+
+    fn set_rip(&mut self, v: u64) {
+        self.cache.rip = v;
+    }
+
+    fn segment(&mut self, index: usize) -> SegmentRegister {
+        self.cache.segs[index]
+    }
+
+    fn efer(&mut self) -> u64 {
+        self.cache.efer
+    }
+
+    fn cr0(&mut self) -> u64 {
+        self.cache.cr0
+    }
+
+    fn rflags(&mut self) -> RFlags {
+        self.cache.rflags
+    }
+
+    fn set_rflags(&mut self, v: RFlags) {
+        self.cache.rflags = v;
+    }
+
     fn instruction_bytes(&self) -> &[u8] {
         let message = self.vp.runner.exit_message();
         match message.header.typ {
@@ -1525,17 +1567,6 @@ impl<T: CpuIo> EmulatorSupport for UhEmulationState<'_, '_, T, HypervisorBackedX
             .expect("set_vp_registers hypercall for setting pending event should not fail");
     }
 
-    fn get_xmm(&mut self, reg: usize) -> Result<u128, Self::Error> {
-        Ok(u128::from_le_bytes(
-            self.vp.runner.cpu_context().fx_state.xmm[reg],
-        ))
-    }
-
-    fn set_xmm(&mut self, reg: usize, value: u128) -> Result<(), Self::Error> {
-        self.vp.runner.cpu_context_mut().fx_state.xmm[reg] = value.to_le_bytes();
-        Ok(())
-    }
-
     fn check_monitor_write(&self, gpa: u64, bytes: &[u8]) -> bool {
         self.vp
             .partition