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kernel+x86_64: implement page fault ISR and scheduler callback
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//! The page fault exception ISR (Interrupt Service Routine). | ||
use core::arch::asm; | ||
use oro_kernel::scheduler::PageFaultType; | ||
use oro_sync::Lock; | ||
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crate::isr! { | ||
/// The ISR (Interrupt Service Routine) for page fault exceptions. | ||
unsafe fn isr_page_fault(kernel, _user_task, err_code) -> Option<Switch> { | ||
let cr2: usize; | ||
// SAFETY: `cr2` is a register that holds the faulting address. It is safe to read. | ||
unsafe { | ||
asm!("mov {}, cr2", out(reg) cr2, options(nostack, preserves_flags)); | ||
} | ||
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// Decode the error code. | ||
// TODO(qix-): Use a register definition for this. | ||
let is_ifetch = err_code & (1 << 4) != 0; | ||
let is_user = err_code & (1 << 2) != 0; | ||
let is_write = err_code & (1 << 1) != 0; | ||
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if !is_user { | ||
panic!("kernel page fault: err={err_code:#032b} cr2={cr2:#016X} core={}", kernel.id()); | ||
} | ||
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let err_type = if is_ifetch { | ||
PageFaultType::Execute | ||
} else if is_write { | ||
PageFaultType::Write | ||
} else { | ||
PageFaultType::Read | ||
}; | ||
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// SAFETY: `event_page_fault` specifies that, in the event we return back to the task, | ||
// SAFETY: that the task has been instructed to re-try the memory operation. x86_64 | ||
// SAFETY: does this by design, so we must do no special handling here. | ||
Some(unsafe { kernel.scheduler().lock().event_page_fault(err_type, cr2) }) | ||
} | ||
} |
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